Age | Commit message (Collapse) | Author | Files | Lines |
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* sparc-desc.h: New file.
* sparc-opc.h: New file.
* decode64.c: New file.
* decode64.h: New file.
* sem64.c: New file.
* cpu64.c: New file.
* cpu64.h: New file.
* model64.h: New file.
* mloop64.in: New file.
* regs64.h: New file.
* trap64.c: New file.
* cpu32.h,decode32.c,decode32.h,model32.c,sem32.c: Rebuild.
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(CPU_OBJS): New variable.
(SIM_OBJS): Add sparc-desc.o.
(SIM_EXTRA_DEPS): Replace cpu-opc.h with sparc-desc.h.
(sim-core.o): Add dev64.h dependency.
(dev64.o): Add rule.
(stamp-arch,stamp-cpu32): Update FLAGS variable, option syntax changed.
(stamp-cpu64): Ditto.
(stamp-desc): New rule.
* configure.in (sim_link_files,sim_link_links): Delete.
Set cpu_objs to one of SPARC32_OBJS,SPARC64_OBJS.
* configure: Rebuild.
* acconfig.h: Rebuild.
* config.in: Rebuild.
* dev64.c: New file.
* dev64.h: New file.
* sparc64.c: New file.
* trap64.h: New file.
* arch.c,arch.h,cpuall.h: Rebuild.
* cpu32.c,decode32.c,decode32.h,model32.c,sem32.c: Rebuild.
* sim-if.c (sparc_disassemble_insn): New function.
(sim_open): sparc_cgen_cpu_open renamed from sparc_cgen_opcode_open.
Set disassembler.
(sim_close): sparc_cgen_cpu_open renamed from sparc_cgen_opcode_open.
* sim-main.h: Don't include cpu-opc.h,cpu-sim.h. Include
sparc-desc.h,sparc-opc.h,sparc-sim.h.
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(stamp-arch,stamp-cpu): Update FLAGS variable, option syntax changed.
(stamp-xmloop): s/-parallel/-parallel-write/.
(stamp-xcpu): Update FLAGS variable, option syntax changed.
* configure.in (sim_link_files,sim_link_links): Delete.
* configure: Rebuild.
* decode.c,decode.h,model.c,sem-switch.c,sem.c: Rebuild.
* decodex.c,decodex.h,modelx.c,semx-switch.c: Rebuild.
* mloop.in (execute): CGEN_INSN_ATTR renamed to CGEN_INSN_ATTR_VALUE.
* sim-if.c (sim_open): m32r_cgen_cpu_open renamed from
m32r_cgen_opcode_open. Set disassembler.
(sim_close): m32r_cgen_cpu_open renamed from m32r_cgen_opcode_open.
* sim-main.h: Don't include cpu-opc.h,cpu-sim.h. Include
m32r-desc.h,m32r-opc.h,m32r-sim.h.
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--with-cgen-sim.
* configure: Rebuild.
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1999-02-05 Frank Ch. Eigler <fche@cygnus.com>
* dv-tx3904sio.c (tx3904sio_tickle): After a polled I/O from the
CPU, start periodic background I/O polls.
(tx3904sio_poll): New function: periodic I/O poller.
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Plus s/sanitize-m32rx/sanitize-cygnus/
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* cpux.h,decodex.c,modelx.c,semx-switch.c: Rebuild.
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(PROFILE_USEFUL_MASK): New macro.
* sim-profile.c (profile_options): Make like trace_options, allow
optional on|off arg where applicable.
(set_profile_option_mask): New function.
(sim_profile_set_option): New function.
(profile_option_handler): Simplify.
Have -p only enable selected things, not everything.
Add missing break to OPTION_PROFILE_PC_RANGE.
* cgen-scache.c (scache_options): Allow optional on|off arg to
--profile-scache.
(scache_option_handler): Use sim_profile_set_option.
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* simops.c (OP_5605): Sign extend MIN32 and MAX32 before saturation
comparison.
(OP_5607): Ditto.
(OP_2A00): Ditto.
(OP_2800): Ditto.
PRs 18435 18436 18437 18439.
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for internal PR 18869 and 18870.
1999-01-26 Frank Ch. Eigler <fche@cygnus.com>
* sim-memopt.c (memory_options): Add MEMORY_FILL option.
(memory_option_handler): Implement MEMORY_FILL option. Make
MEMORY_CLEAR an alias for MEMORY_FILL=0.
(parse_ulong_value): New function.
(do_memopt_add): Allocate all buffers. Optionally fill them.
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* arch.c,arch.h,cpuall.h: Regenerate.
* cpu.c,cpu.h,decode.c,decode.h,model.c,sem-switch.c,sem.c: Regenerate.
* traps.c (sim_engine_invalid_insn): PCADDR->IADDR.
* cpux.c,cpux.h,decodex.c,decodex.h,modelx.c,semx-switch.c: Regenerate.
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(sim_disassemble_insn): Update prototype.
(sim_engine_invalid_insn): Ditto.
* cgen-engine.h (SEMANTIC_FN): Add !WITH_SCACHE version.
(SEM_BRANCH_INIT): PCADDR->IADDR.
(SEM_NBRANCH_FINI): New macro for !WITH_SCACHE case.
* cgen-scache.c (scache_lookup,scache_lookup_or_alloc): PCADDR->IADDR.
* cgen-scache.h (*): Ditto.
* cgen-trace.c (*): Ditto.
* cgen-trace.h (*): Ditto.
* cgen-utils.c (*): Ditto.
* cgen-types.h (integer modes): Use signedNN/unsignedNN types.
(insn_t): Delete.
* genmloop.sh (@cpu@_fill_argbuf): Add !WITH_SCACHE support.
(simple engine framework): Rewrite.
* sim-module.c (modules): Install model module sooner (and in
particular before the profile module).
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* t-sadd.s: New file.
* Makefile.in (TESTS): Add t-sadd.
PR 18438.
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* sim-model.c (sim_mach_lookup_bfd_name): New function.
(sim_model_init): Call it.
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* cpu.h: Regenerate.
* cpux.h: Regenerate.
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start-sanitize-gxsim
1999-01-11 Frank Ch. Eigler <fche@cygnus.com>
* sim-gx-run.c (sim_engine_run): Allay warnings. Write out updated
gx block list after each successful compilation job.
* sim-gx.c (sim_gx_compiled_block_f): dlopen the main executable
image, to allow gx block DLLs to resolve symbols there.
(sim_gx_{read,write}_block_list): Allay warnings.
(sim_gx_block_translate): Allay warnings. Add $GX_FLAGS to
gx compilation/link jobs.
* sim-gx.h: Allay warnings.
end-sanitize-gxsim
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1999-01-11 Frank Ch. Eigler <fche@cygnus.com>
* do-flags.S: New test for parallel PSW update conflicts.
* Makefile.in (TESTS): Run it.
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1999-01-07 Frank Ch. Eigler <fche@cygnus.com>
* do-2wordops.S: New test for sign-extension by ld2h.
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* cpux.h: Regenerate.
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(INCLUDE_DEPS,OPS_INCLUDE_DEPS): Delete.
(sim-if.o): Use SIM_MAIN_DEPS.
(arch.o,traps.o,devices.o): Ditto.
(M32RBF_INCLUDE_DEPS): Use CGEN_MAIN_CPU_DEPS.
(m32r.o,mloop.o,cpu.o,decode.o,sem.o,model.o): Simplify dependencies.
(m32rx.o,mloopx.o,cpux.o,decodex.o,semx.o,modelx.o): Ditto.
(stamp-arch): Pass mach=all to cgen-arch.
* cpu.c,cpu.h,decode.c,model.c,sem-switch.c,sem.c: Regenerate.
* m32r-sim.h (fr30bf_h_cr_[gs]et_handler): Declare.
([GS]ET_H_CR): Define.
(fr30bf_h_psw_[gs]et_handler): Declare.
([GS]ET_H_PSW): Define.
(fr30bf_h_accum_[gs]et_handler): Declare.
([GS]ET_H_ACCUM): Define.
(fr30xf_h_{cr,psw,accum}_[gs]et_handler): Declare.
(fr30bf_h_accums_[gs]et_handler): Declare.
([GS]ET_H_ACCUMS): Define.
* sim-if.c (sim_open): Model probing code moved to sim-model.c.
* m32r.c (WANT_CPU): Define as m32rbf.
(all register access fns): Rename to ..._handler.
* cpux.c,cpux.h,decodex.c,modelx.c,semx.c: Regenerate.
* m32rx.c (WANT_CPU): Define as m32rxf.
(all register access fns): Rename to ..._handler.
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(CGEN_MAIN_SCM): Add rtx-funcs.scm.
(cgen-arch): Pass $(mach) to cgen.sh.
* cgen-engine.h (SEM_BRANCH_FINI): New arg pcvar, all uses updated.
(SEM_BRANCH_INIT_EXTRACT): New macro.
(SEM_BRANCH_INIT): Add taken_p.
(TARGET_SEM_BRANCH_FINI): Provide default definition.
(SEM_BRANCH_FINI): Use it.
(SEM_INSN): Update.
* cgen-run.c (sim_resume): Handle tracing of last insn.
* cgen-scache.h (WITH_SCACHE): Define as 0 if not defined.
* cgen-trace.c (current_abuf): New static global.
(trace_insn_init): Initialize it.
(trace_insn_fini): Use it.
(trace_insn): Set it.
* cgen.sh (arch case): Pass -m ${mach} to cgen.
* genmloop.sh (@cpu@_emit_before): Only define if WITH_SCACHE_PBB.
(@cpu@_emit_after): Ditto.
(simple @cpu@_engine_run_full): New local `pc'. Initialize semantic
labels if WITH_SEM_SWITCH_FULL.
* sim-model.c: Include bfd.h.
(sim_model_init): New function.
(sim_model_install): Record init fn.
* sim-model.h (MACH): New member bfd_name.
* sim-module.c (modules): Initialize model before scache.
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* configure.in: Require autoconf 2.12.1 or higher.
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