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2003-07-262003-07-25 Michael Snyder <msnyder@redhat.com>Michael Snyder12-0/+1346
* pshai.s, pshar.s, pshli.s, pshlr.s: New files. * allinsn.exp: Add psha, pshl tests. * pdec.s, pinc.s, padd.s, paddc.s: New files. * allinsn.exp: Add pdec, pinc, padd, paddc tests. * pand.s, pdmsb.s: New files. * allinsn.exp: Add pand, pdmsb tests.
2003-07-262003-07-08 Michael Snyder <msnyder@redhat.com>Michael Snyder7-0/+856
* allinsn.exp, testutils.inc, add.s, fabs.s, fadd.s, fcmpeq.s, fcmpgt.s, fcnvds.s, fcnvsd.s, fdiv.s, fldi0.s, fldi1.s, flds.s, float.s, fmac.s, fmov.s, fmul.s, fneg.s, frchg.s, fschg.s, fsqrt.s, fsub.s, ftrc.s, shll16.s, shll2.s, shll8.s, shll.s, shlr16.s, shlr2.s, shlr8.s, shlr.s, swap.s: New files.
2003-07-252003-07-25 Michael Snyder <msnyder@redhat.com>Michael Snyder2-6/+12
* gencode.c (pshl): Change < to <= (shift by 16 is allowed). Cast argument of >> to unsigned to prevent sign extension. (psha): Change < to <= (shift by 32 is allowed).
2003-07-252003-07-24 Michael Snyder <msnyder@redhat.com>Michael Snyder2-1/+5
* gencode.c: Fix typo in comment.
2003-07-242003-07-23 Michael Snyder <msnyder@redhat.com>Michael Snyder2-17/+28
* gencode.c: A few more fix-ups of refs and defs. (frchg): Raise SIGILL if in double-precision mode. (ldtlb): We don't simulate cache, so this is a no-op. (movsxy_tab): Correct a few bit pattern errors.
2003-07-232003-07-09 Michael Snyder <msnyder@redhat.com>Michael Snyder2-2/+3
* gencode.c (prnd): Clear LSW of result to zeros.
2003-07-232003-07-23 Michael Snyder <msnyder@redhat.com>Michael Snyder2-0/+37
* pmuls.s: New file.
2003-07-232003-07-09 Michael Snyder <msnyder@redhat.com>Michael Snyder2-3/+4
* gencode.c (pmuls): Expression is mis-parenthesized.
2003-07-232003-07-09 Michael Snyder <msnyder@redhat.com>Michael Snyder3-4/+15
* configure.in: Add testsuite to extra_subdirs for sh. * configure: Regenerate.
2003-07-232003-07-09 Michael Snyder <msnyder@redhat.com>Michael Snyder1-0/+4
* sim/sh: New directory. Tests for Renesas sh family.
2003-07-232003-07-08 Michael Snyder <msnyder@redhat.com>Michael Snyder26-0/+2293
* allinsn.exp, testutils.inc, add.s, fabs.s, fadd.s, fcmpeq.s, fcmpgt.s, fcnvds.s, fcnvsd.s, fdiv.s, fldi0.s, fldi1.s, flds.s, float.s, fmac.s, fmov.s, fmul.s, fneg.s, frchg.s, fschg.s, fsqrt.s, fsub.s, ftrc.s, shll16.s, shll2.s, shll8.s, shll.s, shlr16.s, shlr2.s, shlr8.s, shlr.s, swap.s: New files.
2003-07-232003-07-09 Michael Snyder <msnyder@redhat.com>Michael Snyder2-1/+8
* gencode.c (ppi_gensim): For a conditional ppi insn, if the condition is false, we want to return (not break). A break will take us to the end of the function where registers will be updated, whereas the desired outcome is for nothing to change.
2003-07-232003-06-27 Michael Snyder <msnyder@redhat.com>Michael Snyder2-25/+38
* gencode.c (op tab): Some fix-ups of refs and defs. (ocbi, ocbp): Cache not simulated, but may cause memory fault. (gensym_caselist): Add default case to switch statement. (expand_ppi_code): Add default case to switch statement.
2003-07-232003-06-27 Michael Snyder <msnyder@redhat.com>Michael Snyder2-3/+5
* gencode.c (op tab): Implement movca.l.
2003-07-232003-06-27 Michael Snyder <msnyder@redhat.com>Michael Snyder2-1/+2
* gencode.c (op movsxy_tab): Fix an error in the bit pattern.
2003-07-232003-06-27 Michael Snyder <msnyder@redhat.com>Michael Snyder2-1/+6
* gencode.c (gensim_caselist): The movy instructions use registers R6 and R7 (not R4 and R5 like the movx insns).
2003-07-222003-07-22 Michael Snyder <msnyder@redhat.com>Michael Snyder2-1/+7
* compile.c (sim_resume): Revert 6-24 change, it does not work with gdb breakpoints.
2003-07-182003-07-17 Michael Snyder <msnyder@redhat.com>Michael Snyder2-10/+12
* compile.c (sim_resume): Handle shll reg, reg and shlr reg, reg.
2003-07-182003-07-17 Michael Snyder <msnyder@redhat.com>Michael Snyder2-1/+7
* compile.c (decode): IMM16 is always zero-extended.
2003-07-042003-07-03 Michael Snyder <msnyder@redhat.com>Michael Snyder2-3/+7
* gencode.c (movs): Fix a couple of text transpositions.
2003-07-022003-06-24 Michael Snyder <msnyder@redhat.com>Michael Snyder3-2/+15
* sim-main.h (SIM_WIFSTOPPED, SIM_WSTOPSIG): Define. * compile.c (sim_resume): Use the above to return stop signal.
2003-06-282003-06-27 Michael Snyder <msnyder@redhat.com>Michael Snyder2-5/+8
* gencode.c (op movsxy_tab): Fix up some copy/paste errors in name: s/REG_x/REG_y/.
2003-06-272003-06-27 Michael Snyder <msnyder@redhat.com>Michael Snyder2-2/+6
* gencode.c (op tab): Move misplaced semicolon.
2003-06-232003-06-23 Michael Snyder <msnyder@redhat.com>Michael Snyder2-6/+1
* nrun.c (main): Delete h8/300 ifdef (sim now handles signals).
2003-06-232003-06-23 Michael Snyder <msnyder@redhat.com>Michael Snyder2-2/+6
* sim-reg.c: Fix cut-and-paste bug in comment.
2003-06-222003-06-22 Andrew Cagney <cagney@redhat.com>Andrew Cagney16-99/+6387
Written by matthew green <mrg@redhat.com>, with fixes from Aldy Hernandez <aldyh@redhat.com>, Jim Wilson <wilson@redhat.com>, and Nick Clifton <nickc@redhat.com>. * ppc-instructions: Include altivec.igen and e500.igen. (model_busy, model_data): Add vr_busy and vscr_busy. (model_trace_release): Trace vr_busy and vscr_busy. (model_new_cycle): Update vr_busy and vscr_busy. (model_make_busy): Update vr_busy and vscr_busy. * registers.c (register_description): Add Altivec and e500 registers. * psim.c (psim_read_register, psim_read_register): Handle Altivec and e500 registers. * ppc-spr-table (SPEFSCR): Add VRSAVE and SPEFSCR registers. * configure.in (sim_filter): When *altivec* add "av". When *spe* or *simd* add e500. (sim_float): When *altivec* define WITH_ALTIVEC. When *spe* add WITH_E500. * configure: Re-generate. * e500.igen, altivec.igen: New files. * e500_expression.h, altivec_expression.h: New files. * idecode_expression.h: Update copyright. Include "e500_expression.h" and "altivec_expression.h". * e500_registers.h, altivec_registers.h: New files. * registers.h: Update copyright. Include "e500_registers.h" and "altivec_registers.h". (registers): Add Altivec and e500 specific registers. * Makefile.in (IDECODE_H): Add "idecode_e500.h" and "idecode_altivec.h". (REGISTERS_H): Add "e500_registers.h" and "altivec_registers.h". (tmp-igen): Add dependencies on altivec.igen and e500.igen .
2003-06-222003-06-22 Andrew Cagney <cagney@redhat.com>Andrew Cagney2-36/+31
* interp.c (xfer_mem): Simplify. Only do a single partial transfer. Problem reported by Tom Rix.
2003-06-222003-06-22 Andrew Cagney <cagney@redhat.com>Andrew Cagney3-30/+32
From matthew green <mrg@redhat.com>: * sim-fpu.h: Update copyright. (sim_fpu_fraction, sim_fpu_guard): New prototypes. * sim-fpu.c: Update copyright. (sim_fpu_fraction, sim_fpu_guard): New inline functions.
2003-06-22Oops! Committed to much, reverting :-(Andrew Cagney2-24/+30
2003-06-22Fix changelogAndrew Cagney3-3/+24
2003-06-222003-06-22 Andrew Cagney <cagney@redhat.com>Andrew Cagney3-9/+37
Problems reported by Joshua LeVasseur. * emul_chirp.c: Update copyright. (chirp_emul_nextprop): Return the first property. * hw_htab.c: Update copyright. (htab_decode_hash_table): Fix check for htab size.
2003-06-222003-06-21 Andrew Cagney <cagney@redhat.com>Andrew Cagney2-2/+6
* interrupts.c: Update copyright. (external_interrupt): Fix test for already pending interrupt. Problem found by Joshua LeVasseur.
2003-06-222003-06-21 Andrew Cagney <cagney@redhat.com>Andrew Cagney2-3/+9
* ppc-instructions: Add missing +8 line. Found by blofeldus at yahoo.com.
2003-06-222003-06-21 Andrew Cagney <cagney@redhat.com>Andrew Cagney2-1/+7
From Ian Lance Taylor <ian@airs.com>: * hw_nvram.c (hw_nvram_init_address): Correct call to memset--swap second and third arguments.
2003-06-222003-06-21 Andrew Cagney <cagney@redhat.com>Andrew Cagney2-1/+6
* hw_com.c (hw_com_device_init_data): Check that the output, and not input file opened. Pointed out by masahino tky3.3web.ne.jp.
2003-06-202003-06-17 Doug Evans <dje@sebabeach.org>Frank Ch. Eigler3-3/+9
* cgen-trace.h (sim_disasm_read_memory): Update args to be compatible with disassemble_info:read_memory_func. * cgen-trace.c (sim_disasm_read_memory): Ditto.
2003-06-202003-06-20 Andrew Cagney <cagney@redhat.com>Andrew Cagney6-64/+83
* sim_calls.c (sim_create_inferior): Assert that psim_write_register succeeded. (sim_fetch_register, sim_store_register): Make "regname" constant. Delete Altivec hack. Return result from psim_read_register / psim_write_register. * psim.h (psim_read_register, psim_write_register): Change return type to int. Update comments. * psim.c: Update copyright. (psim_stack): Assert that the psim_read_register worked. (psim_read_register, psim_read_register): Return the register's size. Allocate the cooked buffer dynamically. * hw_register.c: Update copyright. (do_register_init): Check that psim_write_register succeeded. * hw_init.c: Update copyright. (create_ppc_elf_stack_frame, create_ppc_aix_stack_frame): Assert that the register transfer worked.
2003-06-202003-06-19 Andrew Cagney <cagney@redhat.com>Andrew Cagney11-95/+180
* ld-insn.h: Update copyright. (cache_fields): Define. (insn_table_fields): Add insn_field_6 and insn_field_7. (load_insn_table): Pass in the "cache_rules". * ld-insn.c: Update copyright. (load_insn_table): Add parameter "cache_rules". Handle "cache", "computed" and "scratch" fields. (main): Pass "cache_rules" to load_insn_table. * ld-cache.h: Update copyright. (append_cache_table): Declare. * ld-cache.c: Update copyright. (append_cache_table): New function. (load_cache_table): Call. * gen-model.c: Include "ld-cache.h". * gen-itable.c: Include "ld-cache.h". * igen.c: Move #include "ld-cache.h" to earlier. Update copyright. (main): Permit a NULL "cache_rules". Pass address of "cache_rules" to load_insn_table. * Makefile.in (tmp-ld-insn): Add "ld-cache.o". (tmp-igen): Do not include ppc-cache-rules. (gen-itable.o, gen-model.o): Add "ld-cache.h". * ppc-cache-rules: Delete file. * ppc-instructions: Add cache rules.
2003-06-192003-06-19 Andrew Cagney <cagney@redhat.com>Andrew Cagney5-14/+39
* Makefile.in (ICACHE_CFLAGS, SEMANTICS_CFLAGS): Delete. (SIM_FPU_FLAGS): Define. (icache.o): Delete explicit compile command. (semantics.o, idecode.o): Delete explicit compile command. (NOWARN_CFLAGS, STD_CFLAGS): Append SIM_FPU_CFLAGS. * gen-support.c (gen_support_c): Generate #include of "sim-inline.h" and "sim-fpu.h", but conditional on HAVE_COMMON_FPU. * gen-idecode.c (gen_idecode_c): Ditto. * igen.c (gen_icache_c, gen_semantics_c): Wrap #include of "sim-inline.h" and "sim-fpu.h" in HAVE_COMMON_FPU conditional. Move to before "support.h". * Makefile.in, gen-support.c, gen-idecode.c, igen.c: Update copyright.
2003-06-192003-05-30 Alexandre Oliva <aoliva@redhat.com>Michael Snyder20-88/+3830
* allinsn.exp: Fix typos introduced on 2003-05-27. 2003-05-29 Michael Snyder <msnyder@redhat.com> * tas.s: Use er4 for h8h and h8s, er3 for h8sx. 2003-05-28 Michael Snyder <msnyder@redhat.com> * subs.s: New file. * subx.s: New file. * allinsn.exp: Add new subs and subx tests. * testutils.inc: Simplify (and fix) set_carry_flag. (clear_carry_flag, set_zero_flag, clear_zero_flag...): New macros. * addx.s: Use simplified set_carry_flag. 2003-05-27 Michael Snyder <msnyder@redhat.com> * tas.s: New file. * band.s: New file. * biand.s: New file. * allinsn.exp: Add tas, band, biand tests. * brabc.s: Add abs8 test. * bset.s: Add bset/ne, bclr/ne tests. 2003-05-23 Michael Snyder <msnyder@redhat.com> * and.b.s: Add andc exr. * or.b.s: Add orc.exr. * xor.b.s: Add xor exr. * jmp.s: Fix 8-bit indirect test. Add 7-bit vector test. 2003-05-22 Michael Snyder <msnyder@redhat.com> * stack.s: Add rte/l and rts/l tests. * allinsn.exp: Add stack tests. 2003-05-21 Michael Snyder <msnyder@redhat.com> * stack.s: New file: test stack operations. * stack.s: Add bsr, jsr tests. * stack.s: Add trapa, rte tests. * div.s: Corrections for size of dividend. 2003-05-20 Michael Snyder <msnyder@redhat.com> * mul.s: Corrections for unsigned multiply. * div.s: New file, test div instructions. * allinsn.exp: Add div test. 2003-05-19 Michael Snyder <msnyder@redhat.com> * mul.s: New file, test mul instructions. * allinsn.exp: Add mul test.
2003-06-192003-06-18 Michael Snyder <msnyder@redhat.com>Michael Snyder2-89/+167
* compile.c: Replace "Hitachi" with "Renesas". (decode): Distinguish AV_H8S from AV_H8H. (sim_resume): H8SX can use any register for TAS. (decode): Add support for VECIND. (sim_resume): Implement rte/l and rts/l. (GETSR): New macro (actually old macro reincarnated). (decode): Add handling for IMM2. (sim_resume): Drop extra block around jmp, jsr, rts. Add handling for trapa and rte. For divxu.b, change 0xffff mask to 0xff. (set_h8300h): Add bfd_mach_h8300sxn machine.
2003-06-192003-06-18 Corinna Vinschen <vinschen@redhat.com>Michael Snyder2-4/+9
* sim-main.h (enum h8_regnum): Turn around order of MACH, MACL and SBR, VBR (for benefit of gdb).
2003-06-192003-06-05 Michael Snyder <msnyder@redhat.com>Michael Snyder2-6/+33
* compile.c (sim_fetch_register): Handle SBR, VBR, MACH, MACL. (sim_store_register): Ditto.
2003-06-182003-06-17 Richard Sandiford <rsandifo@redhat.com>Chris Demetriou2-2/+6
* mips.igen (do_dmultx): Fix check for negative operands.
2003-06-052003-06-04 Michael Snyder <msnyder@redhat.com>Michael Snyder2-12/+14
* compile.c (sim_info): Fix typo in output. * h8300/compile.c (set_h8300h): Replace 'flag' arguments with a bfd_machine argument, and decode it inline. Check for bfd_mach_h8300hn and bfd_mach_h8300sn.
2003-06-052003-06-04 Michael Snyder <msnyder@redhat.com>Michael Snyder3-27/+20
* common/run.c (main): Remove SIM_H8300 ifdef. (usage): Ditto. * common/sim-options.c (STANDARD_OPTIONS): Add SIM_H8300SX. (standard_options): Add '-x' for h8/300sx. (standard_option_handler): Add case for SIM_H8300SX.
2003-06-042003-06-04 Michael Snyder <msnyder@redhat.com>Michael Snyder2-4/+8
* compile.c (sim_info): Fix typo in output.
2003-06-032003-06-03 Michael Snyder <msnyder@redhat.com>Michael Snyder4-1022/+3400
* h8300/compile.c: Add h8300sx insns and addressing modes. * h8300/sim-main.h: Replaces h8300/inst.h. * h8300/Makefile.in: Tweak to bring in some sim/common stuff.
2003-05-16Use $(SHELL) whenever we invoke move-if-change.Ian Lance Taylor6-88/+107
2003-05-142003-04-13 Michael Snyder <msnyder@redhat.com>Michael Snyder1-0/+4
* sim/h8300: New directory. Tests for Renesas h8/300 family.
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