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The MEMCPY and MEMSET instructions should only examine the low 15 bits of
their length arguments.
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The FT32 simulator was not correctly simulating the behavior of the
program memory (PM) write port. When it is locked, writes to the
data register do nothing.
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2015-09-25 Andrew Bennett <andrew.bennett@imgtec.com>
Ali Lown <ali.lown@imgtec.com>
sim/common/
* sim-bits.h (EXTEND6): New macro.
(EXTEND12): New macro.
(EXTEND25): New macro.
sim/mips/
* Makefile.in (tmp-micromips): New rule.
(tmp-mach-multi): Add support for micromips.
* configure.ac (mips*-sde-elf* | mips*-mti-elf*): Made a multi sim
that works for both mips64 and micromips64.
(mipsisa32r2*-*-*): Made a multi sim that works for mips32 and
micromips32.
Add build support for micromips.
* dsp.igen (do_ph_s_absq, do_w_s_absq, do_qb_s_absq, do_addsc,
do_addwc, do_bitrev, do_extpv, do_extrv, do_extrv_s_h, do_insv,
do_lxx do_modsub, do_mthlip, do_mulsaq_s_w_ph, do_ph_packrl, do_qb_pick
do_ph_pick, do_qb_ph_precequ, do_qb_ph_preceu, do_w_preceq
do_w_ph_precrq, do_ph_qb_precrq, do_w_ph_rs_precrq do_qb_w_raddu,
do_rddsp, do_repl, do_shilov, do_ph_shl, do_qb_shl do_w_s_shllv,
do_ph_shrlv, do_w_r_shrav, do_wrdsp, do_qb_shrav, do_append,
do_balign, do_ph_w_mulsa, do_ph_qb_precr, do_prepend): New functions.
Refactored instruction code to use these functions.
* dsp2.igen: Refactored instruction code to use the new functions.
* interp.c (decode_coproc): Refactored to work with any instruction
encoding.
(isa_mode): New variable
(RSVD_INSTRUCTION): Changed to 0x00000039.
* m16.igen (BREAK16): Refactored instruction to use do_break16.
(JALX32): Add mips32, mips64, mips32r2 and mips64r2 models.
* micromips.dc: New file.
* micromips.igen: New file.
* micromips16.dc: New file.
* micromipsdsp.igen: New file.
* micromipsrun.c: New file.
* mips.igen (do_swc1): Changed to work with any instruction encoding.
(do_add do_addi do_andi do_dadd do_daddi do_dsll32 do_dsra32
do_dsrl32, do_dsub, do_break, do_break16, do_clo, do_clz, do_dclo
do_dclz, do_lb, do_lh, do_lwr, do_lwl, do_lwc, do_lw, do_lwu, do_lhu
do_ldc, do_lbu, do_ll, do_lld, do_lui, do_madd, do_dsp_madd, do_maddu
do_dsp_maddu, do_dsp_mfhi, do_dsp_mflo, do_movn, do_movz, do_msub
do_dsp_msub, do_msubu, do_dsp_msubu, do_mthi, do_dsp_mthi, do_mtlo
do_dsp_mtlo, do_mul, do_dsp_mult, do_dsp_multu, do_pref, do_sc, do_scd
do_sub, do_sw, do_teq, do_teqi, do_tge, do_tgei, do_tgeiu, do_tgeu, do_tlt
do_tlti, do_tltiu, do_tltu, do_tne, do_tnei, do_abs_fmt, do_add_fmt
do_alnv_ps, do_c_cond_fmt, do_ceil_fmt, do_cfc1, do_ctc1, do_cvt_d_fmt
do_cvt_l_fmt, do_cvt_ps_s, do_cvt_s_fmt, do_cvt_s_pl, do_cvt_s_pu
do_cvt_w_fmt, do_div_fmt, do_dmfc1b, do_dmtc1b, do_floor_fmt, do_luxc1_32
do_luxc1_64, do_lwc1, do_lwxc1, do_madd_fmt, do_mfc1b, do_mov_fmt, do_movtf
do_movtf_fmt, do_movn_fmt, do_movz_fmt, do_msub_fmt, do_mtc1b, do_mul_fmt
do_neg_fmt, do_nmadd_fmt, do_nmsub_fmt, do_pll_ps, do_plu_ps, do_pul_ps
do_puu_ps, do_recip_fmt, do_round_fmt, do_rsqrt_fmt, do_prefx, do_sdc1
do_suxc1_32, do_suxc1_64, do_sqrt_fmt, do_sub_fmt, do_swc1, do_swxc1
do_trunc_fmt): New functions, refactored from existing instructions.
Refactored instruction code to use these functions.
(RSVD): Changed to use new reserved instruction.
(loadstore_ea, not_word_value, unpredictable, check_mt_hilo, check_mf_hilo,
check_mult_hilo, check_div_hilo, check_u64, do_luxc1_32, do_sdc1, do_suxc1_32,
check_fmt_p, check_fpu, do_load_double, do_store_double): Added micromips32
and micromips64 models.
Added include for micromips.igen and micromipsdsp.igen
Add micromips32 and micromips64 models.
(DecodeCoproc): Updated to use new macro definition.
* mips3264r2.igen (do_dsbh, do_dshd, do_dext, do_dextm, do_dextu, do_di,
do_dins, do_dinsm, do_ei, do_ext, do_mfhc1, do_mthc1, do_ins, do_dinsu,
do_seb, do_seh do_rdhwr, do_wsbh): New functions.
Refactored instruction code to use these functions.
* sim-main.h (CP0_operation): New enum.
(DecodeCoproc): Updated macro.
(IMEM32_MICROMIPS, IMEM16_MICROMIPS, MICROMIPS_MINOR_OPCODE,
MICROMIPS_DELAYSLOT_SIZE_ANY, MICROMIPS_DELAYSLOT_SIZE_16, MICROMIPS_DELAYSLOT_SIZE_32,
ISA_MODE_MIPS32 and ISA_MODE_MICROMIPS): New defines.
(sim_state): Add isa_mode field.
sim/testsuite/sim/mips/
* basic.exp (run_micromips_test, run_sim_tests): New functions
Add support for micromips tests.
* hilo-hazard-4.s: New file.
* testutils.inc (_dowrite): Changed reserved instruction encoding.
(writemsg): Moved the la and li instructions before the data they are
assigned to, which prevents a bug where MIPS32 relocations are used instead
of micromips relocations when building for micromips.
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The FT32 simulator has character output, of course. This patch
adds character input, which lets the simulator run interactive
FT32 applications, e.g. language interpreters.
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* gdb-if.c (sim_info): Stub function to allow GDB to be built
with this simulator.
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* armcopro.c: Remove extraneous whitespace.
* armdefs.h: Likewise.
* armfpe.h: Likewise.
* arminit.c: Likewise.
* armopts.h: Likewise.
* armos.c: Likewise.
* armos.h: Likewise.
* armrdi.c: Likewise.
* armsupp.c: Likewise.
* armvirt.c: Likewise.
* bag.c: Likewise.
* bag.h: Likewise.
* communicate.c: Likewise.
* communicate.h: Likewise.
* dbg_conf.h: Likewise.
* dbg_cp.h: Likewise.
* dbg_hif.h: Likewise.
* dbg_rdi.h: Likewise.
* gdbhost.c: Likewise.
* gdbhost.h: Likewise.
* iwmmxt.c: Likewise.
* iwmmxt.h: Likewise.
* kid.c: Likewise.
* main.c: Likewise.
* maverick.c: Likewise.
* parent.c: Likewise.
* thumbemu.c: Likewise.
* wrapper.c: Likewise.
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* Makefile.in (SIM_EXTRA_CFLAGS): Revert previous delta.
(SIM_EXTRA_LIBS): Add -lm.
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* Makefile.in (SIM_EXTRA_CFLAGS): Add -lm.
* armdefs.h (ARMdval, ARMfval): New types.
(ARM_VFP_reg): New union.
(struct ARMul_State): Add VFP_Reg and FPSCR fields.
(VFP_fval, VFP_uword, VFP_sword, VFP_dval, VFP_dword): Accessor
macros for the new VFP_Reg field.
* armemu.c (handle_v6_insn): Add code to handle MOVW, MOVT,
QADD16, QASX, QSAX, QSUB16, QADD8, QSUB8, UADD16, USUB16, UADD8,
USUB8, SEL, REV, REV16, RBIT, BFC, BFI, SBFX and UBFX
instructions.
(handle_VFP_move): New function.
(ARMul_Emulate16): Add checks for newly supported v6
instructions. Add support for VMRS, VMOV and MRC instructions.
(Multiply64): Allow nRdHi == nRm and/or nRdLo == nRm when
operating in v6 mode.
* armemu.h (t_resolved): Define.
* armsupp.c: Include math.h.
(handle_VFP_xfer): New function. Handles VMOV, VSTM, VSTR, VPUSH,
VSTM, VLDM and VPOP instructions.
(ARMul_LDC): Test for co-processor 10 or 11 and pass call to the
new handle_VFP_xfer function.
(ARMul_STC): Likewise.
(handle_VFP_op): New function. Handles VMLA, VMLS, VNMLA, VNMLS,
VNMUL, VMUL, VADD, VSUB, VDIV, VMOV, VABS, VNEG, VSQRT, VCMP,
VCMPE and VCVT instructions.
(ARMul_CDP): Test for co-processor 10 or 11 and pass call to the
new handle_VFP_op function.
* thumbemu.c (tBIT, tBITS, ntBIT, ntBITS): New macros.
(test_cond): New function. Tests a condition and returns non-zero
if the condition has been met.
(handle_IT_block): New function.
(in_IT_block): New function.
(IT_block_allow): New function.
(ThumbExpandImm): New function.
(handle_T2_insn): New function. Handles T2 thumb instructions.
(handle_v6_thumb_insn): Add next_instr and pc parameters.
(ARMul_ThumbDecode): Add support for IT blocks. Add support for
v6 instructions.
* wrapper.c (sim_create_inferior): Detect a thumb address and call
SETT appropriately.
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Everyone has migrated to the split functions (trace_prefix + trace_generic)
a while ago, so we can drop this one now.
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Rather than redirect using a define, just rename the symbol fully.
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The bfin/msp430 ports already had trace logic set up for reading/writing
cpu registers, albeit using different unrelated levels (core & vpu). Add
a proper register class for these and for other ports.
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Some code paths trace on a system instance and not a cpu instance (like
the events code), so add some helpers for those cases.
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Make the acronyms clear for people.
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This helper macro has largely the same behavior as libiberty's lbasename.
There is a slight nuance related to colons, but it's not clear what the
point of that is, and the code implies that it just wants the basename.
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This helps standardize the configure --help output.
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Since --trace-debug is for people hacking on the sim sources rather than
people just using the sim, default it to off. This matches the behavior
of other debug knobs we have.
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Assume the build system supports stdint.h/stdarg.h as those have been
around long enough and we don't care about pre-stdc compilers anymore.
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If the configured in default doesn't match a known value, throw an
assertion failure rather than segfaulting deeper down.
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Let's assume that the system supports the POSIX int8/16/32/64_t types
as this collapses the logic significantly.
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We use SIM_xxx_H in most headers, so convert _SIM_xxx_H_ over to it.
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Since we always include the raw syscall number when tracing, also
including it in the name when it's unknown is redundant. Simplify
the code by using a constant string.
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The new helpers for walking the maps tested the wrong value for exiting
the for loop. This caused crashes when looking up entries that were not
in the map.
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Many ports have the same sim syscall logic, so add some helpers to handle
all the common details. The arches still have to deal with the unpacking
and packing of the syscall arguments, but the rest of the sim<->callback
glue is now shared.
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Almost every port implements these two callbacks in the same way, so
unify them in the common layer.
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When tracing, we often want to display the human readable name for the
various syscall/errno values. Rather than make each target duplicate
the lookup, extend the existing maps to include the string directly,
and add helper functions to look up the constants.
While most targets are autogenerated (from libgloss), the bfin/cris
targets have custom maps for the Linux ABI which need to be updated
by hand.
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A few places still refer to the configure.in file; update them.
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No code uses this anymore and the symbol conflicts with the new TRACE
helper. Punt it from configure.
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Replace the "if (TRACE_xxx_P) trace_generic" form with "TRACE_xxx".
The output is the same, but the code is nicer to read.
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Now that there's common helpers for printing trace data, switch to that
to restore the insn tracing support for this target.
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The Blackfin port had some TRACE_xxx macros for easily logging trace data.
Use these as a base for common ones that have a simple form and match the
existing sets of helper macros.
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We want to add new common trace helpers including "TRACE", so change the
mips one to the new WITH_TRACE_ANY_P macro since they do the same thing.
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We have STRACE_ANY_P and TRACE_ANY_P, so add WITH_TRACE_ANY_P to fill
out the API. This lets us wrap the internal configure symbol.
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We want to add new common trace helpers including "TRACE", so rename the
moxie one to MOXIE_TRACE_INSN. This also matches what the code is doing.
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The cgen code declares some macros/funcs using the trace_xxx prefix, but
the code isn't generic and only works with cgen targets. This is blocking
the creation of new common trace functions.
Let's blindly add cgen_xxx prefixes to all these symbols. Some already
use this convention to avoid conflicts, so it makes sense to align them.
In the future we might want to move some to the common trace core, but
one thing at a time.
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These macros were copied from the Blackfin port but never used, so delete
them as part of the trace unification work.
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First we convert the ETRACE_P to STRACE_EVENTS_P. This means we move from
using the sim_events.trace storage to the common sim_state_base.trace_data
array. With that deleted, the common trace init code can be simplified so
the sim state works the same as the sim cpu.
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These are the parallel to the TRACE_xxx_P macros and fill out the full
set to match the existing debug one.
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No point in duplicating the shift logic when we have macros already to
keep that all unified.
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This way we can use the IDX macros everywhere and not worry about the
encoding of the WITH_TRACE define in multiple places.
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This is the only sim that sets up its own WITH_TRACE mask and it conflicts
with the user setting their own list at configure time. Drop it to match
all the other sims.
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The interrupts.c file has a static/fuller definition that is used,
so drop this copy in interp.c.
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This code already matched the common sim reusme logic, so we can simply
drop it and pull in the common code.
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Only one place used get_word/put_word, so inline the usage there.
All the rest is dead code so trim it.
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The syscall path was the only code checking the custom exception state
after recent cleanups. Once we change that to the common engine halt
function, we can delete that state entirely.
This also helps highlight some other dead code that we can cull.
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No point in open coding this logic here when we have common size types
already that give the right answer.
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The sim-inline.h header already takes care of this for us, so punt
the local definitions.
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This allows us to use the common code for all exception handling.
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