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2000-07-272000-06-25 Stephane Carrez <Stephane.Carrez@worldnet.fr>Andrew Cagney3-2/+9
2000-07-272000-06-25 Stephane Carrez <Stephane.Carrez@worldnet.fr>Andrew Cagney5-0/+39
2000-07-272000-06-25 Stephane Carrez <Stephane.Carrez@worldnet.fr>Andrew Cagney2-1/+17
2000-07-27Add m68hc11 configry.Andrew Cagney5-0/+4366
2000-07-27New simulator.Andrew Cagney16-0/+7449
2000-07-27From 2000-06-25 Stephane Carrez <Stephane.Carrez@worldnet.fr>:Andrew Cagney4-2/+126
2000-07-27* compile.c (decode): Distinguish inc/dec.[wl] and adds/subsAndrew Cagney2-1/+11
2000-07-20* m16.igen (break): Call SignalException not sim_engine_halt.Andrew Cagney2-1/+5
2000-07-142000-07-14 Fernando Nasser <fnasser@cygnus.com>Fernando Nasser2-1/+5
2000-07-142000-07-14 Fernando Nasser <fnasser@cygnus.com>Fernando Nasser2-0/+9
2000-07-05Change minimum loop size limit to 0x10 (103792)Nick Clifton2-1/+5
2000-07-04* armvirt.c (ABORTS): Do not define.Alexandre Oliva2-1/+3
2000-07-04* armdefs.h (struct ARMul_State): Add is_StrongARM.Alexandre Oliva5-11/+59
2000-07-04* armemu.c (ARMul_Emulate, t_undefined): Proceed to next insn.Alexandre Oliva2-1/+3
2000-07-04* armemu.h (INSN_SIZE): New macro.Alexandre Oliva4-45/+48
2000-07-04* armemu.c (LoadSMult): Use WriteR15() to discard the leastAlexandre Oliva2-2/+5
2000-07-04* armemu.h (WRITEDESTB): New macro.Alexandre Oliva3-37/+48
2000-07-04* armemu.h (GETSPSR): Call ARMul_GetSPSR().Alexandre Oliva3-4/+18
2000-07-04* armemu.h (PSR_FBITS, PSR_SBITS, PSR_XBITS, PSR_CBITS): New.Alexandre Oliva4-30/+40
2000-07-04* armemu.c (ARMul_Emulate): Compute writeback value beforeAlexandre Oliva2-8/+20
2000-07-04* armdefs.h (SYSTEMBANK): Define as USERBANK.Alexandre Oliva3-8/+6
2000-07-04TIc80 simulator.Andrew Cagney18-1/+8613
2000-07-04Fix MOVN.fmt and MOVZ.fmt, need to test GPR[RT].Andrew Cagney2-14/+14
2000-06-24* verbosity reductionFrank Ch. Eigler2-2/+5
2000-06-24* build cleanliness fixFrank Ch. Eigler2-1/+6
2000-06-23Fix printf arguments.Andrew Cagney2-3/+8
2000-06-22* armemu.c (Multiply64): Fix computation of flag N.Alexandre Oliva2-4/+5
2000-06-22* armemu.c (MultiplyAdd64): Fix computation of flag N.Alexandre Oliva2-4/+7
2000-06-20* build fixFrank Ch. Eigler2-21/+11
2000-06-20* armemu.h (NEGBRANCH): Do not overwrite the two most significantAlexandre Oliva2-1/+6
2000-06-19Add strongarm testsNick Clifton2-1/+10
2000-06-13* "Dont" -> "Don't"Frank Ch. Eigler3-2/+6
2000-06-132000-06-13 Kazu Hirata <kazu@hxi.com>Jeff Law2-47/+36
2000-06-07sh-dsp support, simulator speedup by using host byte order:Joern Rennecke1-1/+4
2000-05-30Remove illegal instruciton pattern, since it is the same as the breakpointNick Clifton2-7/+5
2000-05-30Add support for v4 SystemMode.Nick Clifton11-57/+159
2000-05-29Define GPR_CLEARNick Clifton2-0/+15
2000-05-29fix spelling mistake in commentNick Clifton1-1/+1
2000-05-29Remove RCS tags to make synchronisation easier.Nick Clifton1-3/+0
2000-05-29Use GPR_CLEAR instead of GPR_SETNick Clifton2-1/+6
2000-05-29replace GPR_SET with GPR_CLEARNick Clifton2-1/+6
2000-05-29minor formatting tweaks to aid syncronisationNick Clifton2-8/+17
2000-05-24Change profiling so that it is enabled by default. Re-generate everything.Andrew Cagney43-2307/+2582
2000-05-23Add special case handling when GDB set CPSR registerNick Clifton2-1/+12
2000-05-23sigrc wasn't initialized before being passed to sim_resume().Andrew Cagney2-0/+6
2000-05-22* am33.igen: Fix leading comments of SP-relative offset insns thatAlexandre Oliva2-7/+11
2000-05-18* mn10300_sim.h (genericAdd, genericSub, genericCmp, genericOr,Alexandre Oliva5-167/+175
2000-05-15sh-dsp support, simulator speedup by using host byte order:Joern Rennecke3-801/+2226
2000-05-08* merge from internal treeFrank Ch. Eigler2-4/+20
2000-05-03Add missing ChangeLog.Andrew Cagney2-1/+25
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