Age | Commit message (Collapse) | Author | Files | Lines |
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* frv.cpu (nsdiv, nudiv, nsdivi, nudivi): Remove fr400 profiling unit.
(scutss): Change unit to I0.
(calll, callil, ccalll): Add missing FR550-MAJOR and profile unit.
(mqsaths): Fix FR400-MAJOR categorization.
(media-quad-multiply-cross-acc, media-quad-cross-multiply-cross-acc)
(media-quad-cross-multiply-acc): Change unit from MDUALACC to FMALL.
* frv.opc (fr400_check_insn_major_constraints): Check for (M-2,M-1)
combinations.
opcodes/
* frv-desc.c, frv-opc.c: Regenerate.
sim/frv/
* cache.c (frv_cache_init): Change fr400 cache statistics to match
the fr405.
(non_cache_access): Add missing breaks.
* interrupts.c (set_exception_status_registers): Always set EAR15
for data_access_errors.
* memory.c (fr400_check_write_address): Remove redundant alignment
check.
* model.c: Regenerate.
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* frv.c (frvbf_iacc_cut): Rework, taking rounding into account.
testsuite/
* sim/frv/fr400/scutss.cgs: Fix tests to account for rounding.
Add some new ones.
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* frv.cpu (r-store, r-store-dual, r-store-quad): Delete.
(rstb, rsth, rst, rstd, rstq): Delete.
(rstbf, rsthf, rstf, rstdf, rstqf): Delete.
gas/testsuite/
* gas/frv/allinsn.s (rstb, rsth, rst, rstd, rstq): Replace with nops.
(rstbf, rsthf, rstf, rstdf, rstqf): Likewise.
* gas/frv/allinsn.d: Update accordingly.
opcodes/
* frv-desc.c, frv-opc.c, frv-opc.h: Regenerate.
sim/frv/
* decode.c, decode.h, model.c, sem.c: Regenerate.
sim/testsuite/
* sim/frv/{rstb,rsth,rst,rstd,rstq}.cgs: Delete.
* sim/frv/{rstbf,rsthf,rstf,rstdf,rstqf}.cgs: Delete.
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* gencode.c (movua.l): Set thislock to 0, not n.
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* and.s, movi.s, sett.s: New files.
* allinsn.exp: Add new tests.
* testutils.inc (set_sr_bit): Fix macro labels.
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* gencode.c (table): Change from char to short.
(dumptable): Change generated table from char to short.
* interp.c (sh_jump_table, sh_dsp_table, ppi_table): char to short.
(init_dsp): Compute size of sh_dsp_table.
(sim_resume): Change jump_table from char to short.
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Committed by Andrew Cagney.
* mloopx.in: Update copyright.
(xextract-pbb): Fixed trap for system calls operation in parallel.
* mloop2.in (xextract-pbb): Ditto.
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* gencode.c: (op tab): Some refs and defs fixes.
"fsrra" -> "fsrra <FREG_N>".
"sleep": replace array ref with array addr.
"trapa": ditto.
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* gencode.c: Comment and whitespace clean-ups.
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* ppc-instructions: Update copyright.
(convert_to_integer): Add trailing ";" to label.
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2004-01-26 Chris Demetriou <cgd@broadcom.com>
* configure.in (mips*-*-*): Configure in testsuite.
* configure: Regenerate.
[ sim/testsuite/ChangeLog ]
2004-01-26 Chris Demetriou <cgd@broadcom.com>
* sim/mips: New directory. Tests for the MIPS simulator.
[ sim/testsuite/sim/mips/ChangeLog ]
2004-01-26 Chris Demetriou <cgd@broadcom.com>
* basic.exp: New file.
* testutils.inc: New file.
* sanity.s: New file.
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test passes.
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* mips.igen (check_mf_cycles, check_mt_hilo, check_mf_hilo)
(check_mult_hilo): Improve comments.
(check_div_hilo): Likewise. Also, fork off a new version
to handle mips32/mips64 (since there are no hazards to check
in MIPS32/MIPS64).
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* gencode.c: Whitespace cleanup.
* interp.c: Ditto.
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* dmxy.s, fipr.s, fpchg.s, ldrc.s, loop.s, movli.s, movua.s,
movxy.s, pabs.s, pclr.s, prnd.s, psub.s, pswap.s: New files.
* allinsn.exp: Add new tests.
* testutils.inc (set_sr_bit): Add argument.
(set_greg): Add .align directives.
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* gencode.c: Replace 'Hitachi' with 'Renesas'.
(op tab): Add new instructions for sh4a, DBR, SBR.
(expand_opcode): Add handling for new movxy combinations.
(gensym_caselist): Ditto.
(expand_ppi_movxy): Remove movx/movy expansions,
now handled in expand_opcode.
(gensym): Add some helpful macros.
(expand_ppi_code): Flatten loop for simplicity, tweak for 12-bit
instead of 8-bit table (some insns are ambiguous to 8 bits).
(ppi_gensim, main): Generate 12-bit instead of 8-bit ppi table.
* interp.c: Replace 'Hitachi' with 'Renesas'.
(union saved_state_type): Add dbr, sgr, ldst.
(get_loop_bounds_ext): New function.
(init_dsp): Add bfd_mach_sh4al_dsp.
(sim_resume): Handle extended loop bounds.
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* gencode.c (expand_opcode): Simplify and reorganize.
Eliminate "shift" parameter. Eliminate "4 bits at a time"
assumption. Flatten switch statement to a single level.
Add "eeee" token for even-numbered registers.
(bton): Delete.
(fsca): Use "eeee" token.
(ppi_moves): Rename to "expand_ppi_movxy". Do the ddt
[movx/movy] expansion here, as well as the ppi expansion.
(gensim_caselist): Accept 'eeee' along with 'nnnn'.
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* compile.c (sim_load): Don't pass a type to bfd_openr.
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(O_RDONLY): Do not define.
(O_WRONLY): Likewise.
(O_RDWR): Likewise.
(targ-vals.h): Include it.
(translate_open_mode): Use TARGET_O_* instead of O_*.
(SWIopen): Likewise.
* Makefile.in (armos.o): Depend on targ-vals.h.
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Patch submitted by Anil Paranjape <AnilP1@KPITCummins.com>
* sim-main.h (H8300H_MSIZE): Increase from 18 bits to 24 bits.
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* Makefile.in : Add new machine m32r2.
* m32r2.c : New file for m32r2.
* mloop2.in : Ditto
* model2.c : Ditto
* sem2-switch.c : Ditto
* m32r-sim.h : Add EVB register.
* sim-if.h : Ditto
* sim-main.h : Ditto
* traps.c : Ditto
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(SPR_REGNUM_MAX): Delete.
* frv.c (gdb/sim-frv.h): Include.
(frvbf_fetch_register, frvbf_store_register): Use register number
constants from gdb/sim-frv.h. Check availability of general
purpose and float registers.
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variants.
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* cache.c (address_interference): Check for higher priority requests
in the same pipeline.
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* gencode.c (tab): Add entries for fsca and fsrra.
(expand_opcode): Allow variable length n / m fields.
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* frv-sim.h (REGNUM_LR): Removed.
(REGNUM_SPR_MIN,REGNUM_SPR_MAX): New macros.
* frv.c (frvbf_fetch_register): Fetch SPR registers based on
REGNUM_SPR_MIN and REGNUM_SPR_MAX. Check whether SPRs are implemented.
Return 0 for an unimplemented register. Return the length of the data
for an implemented register.
(frvbf_store_register): Ditto.
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2003-10-30 Andrew Cagney <cagney@redhat.com>
* traps.c: Replace "struct symbol_cache_entry" with "struct
bfd_symbol".
Index: sim/d10v/ChangeLog
2003-10-30 Andrew Cagney <cagney@redhat.com>
* simops.c: Replace "struct symbol_cache_entry" with "struct
bfd_symbol".
Index: sim/common/ChangeLog
2003-10-30 Andrew Cagney <cagney@redhat.com>
* sim-trace.c, sim-base.h: Replace "struct symbol_cache_entry"
with "struct bfd_symbol".
Index: ld/ChangeLog
2003-10-30 Andrew Cagney <cagney@redhat.com>
* emultempl/pe.em, pe-dll.c: Replace "struct symbol_cache_entry"
with "struct bfd_symbol".
Index: bfd/ChangeLog
2003-10-30 Andrew Cagney <cagney@redhat.com>
* syms.c: Replace "struct symbol_cache_entry" with "struct
bfd_symbol".
* vms.h, targets.c, section.c, reloc.c, peicode.h: Ditto.
* mipsbsd.c, elf.c, linker.c, elf-bfd.h, ecoff.c: Ditto.
* cpu-z8k.c, cpu-ns32k.c, cpu-h8500.c, bfd.c, bfd-in.h: Ditto.
* bfd-in2.h: Re-generate.
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* callback.c (os_truncate): Call "truncate", and not "stat".
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* targets.c: Replace "struct sec" with "struct bfd_section"
* syms.c, sparclynx.c, section.c, opncls.c: Ditto.
* libcoff-in.h, libbfd-in.h, elfxx-target.h: Ditto.
* elf.c, coffgen.c, bfd.c, bfd-in.h, aoutf1.h: Ditto.
* aout-tic30.c, aout-target.h:
* bfd-in2.h, libcoff.h, libbfd.h: Regenerate.
Index: binutils/ChangeLog
2003-10-19 Andrew Cagney <cagney@redhat.com>
* coffgrok.h (coff_section): Replace 'struct sec" with "struct
bfd_section".
Index: gdb/ChangeLog
2003-10-19 Andrew Cagney <cagney@redhat.com>
* symtab.c: Replace "struct sec" with "struct bfd_section".
* objfiles.c, linespec.c, blockframe.c, block.c: Ditto.
Index: ld/ChangeLog
2003-10-19 Andrew Cagney <cagney@redhat.com>
* pe-dll.c: Replace "struct sec" with "struct bfd_section".
Index: sim/common/ChangeLog
2003-10-19 Andrew Cagney <cagney@redhat.com>
* sim-base.h: Replace "struct sec" with "struct bfd_section".
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* h8300/compile.c : Addition of extern variable h8300_normal_mode
(SP) : Handle normal mode
(bitfrom) : Use normal mode flag to return suitable value
(lvalue) : Use normal mode flag to return command line location
(decode) : Decode instruction correctly for normal mode
(init_pointers) : Initialise memory correctly for normal mode
(sim_resume) : Handle cases for normal mode using h8300_normal_mode flag
(sim_store_register) : Handle 2 byte PC for normal mode
(sim_fetch_register) : Handle 2 byte PC for normal mode
(set_h8300h) : Set normal mode flag as per architechture
(sim_load) : Allocate 64K for normal mode instead of bigger memory
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* emul_netbsd.c: Only a comment may follow an #endif.
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* Makefile.in (sim_calls.o): No longer depends on gdb/tm.h.
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* callback.h (struct host_callback_struct): New members ftruncate
and truncate.
gdb:
sim/common:
* callback.c (os_ftruncate, os_truncate): New functions.
(default_callback): Initialize ftruncate and truncate members.
sim/sh:
* syscall.h (SYS_truncate, SYS_ftruncate): Define.
* interp.c (trap): Add support for SYS_ftruncate and SYS_truncate.
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Use bfd_section_size and bfd_get_section_vma.
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* sim/frv/testutils.inc (or_gr_immed): New macro.
* sim/frv/fp_exception-fr550.cgs: Write insns using
unaligned registers into the program in order to
cause the required exceptions.
* sim/frv/fp_exception.cgs: Ditto.
* sim/frv/regalign.cgs: Ditto.
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* cpu.h, sem.c: Regenerate.
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* configure.in: Move frv handling to alphabetically correct placement.
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* sim/frv/fr550: New subdirectory.
* sim/frv/fr400/*.cgs: Add fr550 as appropriate.
* sim/frv/fr500/*.cgs: Add fr550 as appropriate.
* sim/frv/interrupts/*.cgs: Add fr550 as appropriate.
* sim/frv/interrupts/*-fr550.cgs: New test cases for fr550.
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