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2013-06-28* rx.c (SHIFT_OP): A shift by zero still sets the condition codes.Nick Clifton2-2/+6
2013-06-26 * Makefile.in (dtbdir): Don't use gdb's version.in.Tom Tromey2-1/+5
2013-06-24Adapt sim to new version number & date locations.Joel Brobecker5-11/+51
This change is required now that gdb/version.in has been moved to gdb/common/version.in and now that the date needs to be fetched from bfd/version.h. sim/common/ChangeLog: * create-version.sh: New script. Adapted from gdb/commong/create-version.sh. * Make-common.in (version.c): Update rule dependencies, and re-implement using create-version.sh. sim/ppc/ChangeLog: * Makefile.in (srccom): New variable. (version.c): Update rule dependencies, and re-implement using sim/common/create-version.sh.
2013-06-24sim: bfin: note missing parallel handling of SEARCHMike Frysinger2-0/+18
The SEARCH insn is an oddball when it comes to parallel usage. It places a big limit on what other insns it can run in parallel with, but we don't currently track the amount of state needed to verify this (since no other insn really requires this). Add a note for now in case we get around to it.
2013-06-24sim: bfin: handle invalid HLs encoding in dsp shift insnsMike Frysinger2-5/+16
For many of the 32bit dsp shift related insns, we were just ignoring the HLs field. The hardware does not though and will reject the insn if it's set incorrectly. Update the sim to match.
2013-06-24sim: bfin: run-tests.sh: fix typo in usage exitMike Frysinger2-1/+5
2013-06-24sim: bfin: se_all32bitopcodes: skip debug insns under the simMike Frysinger2-1/+18
Since the sim has a few fake debug insns that the hardware does not, we need to check for those before attempting to run them. Otherwise we'll randomly trigger the sim debug asserts/aborts/halts insns. On the hardware, these are proper invalid insns, and the table catches that.
2013-06-24sim: bfin: speed up all insn testcases slightlyMike Frysinger2-2/+8
The main body of the "all insn" test is executed once per tested insn, and we test millions of insns here. Any shrinkage we can do in this loop will speed things up nicely (since it's multiplied per tested insn). To that end, simplify the end-of-table test into one less insn, and omit the SSYNC when we build for the sim. When we build to run on the hardware, this insn matters, but the sim doesn't have write store buffers in the chip that might get in the way (memory writes are atomic).
2013-06-23sim: bfin: trim trailing whitespaceMike Frysinger2-1/+5
2013-06-21 * msp430: New Directory.Nick Clifton17-0/+8534
* configure.tgt: Add it. * configure: Regenerate. * gennltvals.sh: Add msp430 support. * nltvals.def: Regenerate. * Makefile.in: New. * aclocal.m4: Generate. * config.in: Generate. * configure.ac: New. * configure: Generate. * msp430-sim.c: New. * msp430-sim.h: New. * sim-main.h: New. * trace.c: New. * trace.h: New.
2013-06-19sim: bfin: stricter insn decodingMike Frysinger2-50/+86
We wrote a test case that tries every single 32bit opcode on the hardware and compared it to the sim. There were a bunch of places in the sim where we weren't strict enough (requiring certain parts of the opcode be set) so we were treating a lot of invalid opcodes as valid ones. This sprinkles out a lot additional checks in the dsp32alu class. Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2013-06-17sim: bfin: tweak run-tests for parallel usageMike Frysinger2-6/+34
2013-06-17sim: bfin: add helpful info for generating test tablesMike Frysinger2-0/+23
2013-06-17sim: bfin: drop RET[ENI] setupMike Frysinger2-3/+4
Since these insns run in usermode, there should be no need to setup RET[ENI] to safe values. They won't be dereferenced, and any insn that returns via them are valid only in supervisor mode. Since this is in the main exception code path, saving any insn at all is good as it gets multiplied quickly (as in O(n^2) times). Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2013-06-17sim: bfin: add flush/HWERR todoMike Frysinger2-0/+8
2013-06-10sim: bfin: only regen linux-fixed-code.h in maintainer modeMike Frysinger2-1/+6
Since many people don't have a Blackfin toolchain available, only try to regenerate the header file when in maintainer mode. This file rarely changes, and when it does, we commit the generated output, so there's almost never a need to run directly on an end system.
2013-06-05sim: use AM_MAINTAINER_MODEMike Frysinger76-337/+1802
I noticed the sim code is using an old implementation of the maintainer logic. I cut it over to the new macro (like gdb has been doing). In practice, it makes no difference currently as nothing in the sim tree uses it, but I have a follow up commit for the Blackfin tree that needs it.
2013-05-15sim: arm: add support for MOVW and MOVT instructionsMike Frysinger4-4/+71
From: Jayant R. Sonar <Jayant.Sonar@kpitcummins.com> This patch adds simulator support for handling the armv7 instructions 'movw (immediate)' and 'movt'. Compiler frequently use these instructions to load the 32bit addresses of global variables, string pointers etc. into the general registers. In absence of support of these instructions: 1. GDB run simulator fails to print even simple "hello world" string on console. 2. Loading of global variable addresses into the registers fail causing arithmetic operation failures. Patch has been regression tested for arm-none-eabi (-march=armv7-a).
2013-05-13 * v850.igen (LDSR): Accept but ignore a selID parameter.Nick Clifton2-3/+9
2013-05-10gdbTom Tromey20-10/+62
Freddie Chopin <freddie_chopin@op.pl> PR build/15414: * configure: Rebuild. * configure.ac (build_warnings): Do not use -Wformat-nonliteral with -Wno-format. sim/common * acinclude.m4 (SIM_AC_OPTION_WARNINGS): Do not use -Wformat-nonliteral with -Wno-format. sim/bfin * configure: Rebuild. sim/cr16 * configure: Rebuild. sim/cris * configure: Rebuild. sim/d10v * configure: Rebuild. sim/igen * configure: Rebuild. sim/m68hc11 * configure: Rebuild. sim/mips * configure: Rebuild. sim/mn10300 * configure: Rebuild. sim/v850 * configure: Rebuild.
2013-05-06Move ChangeLog entry from sim/ to sim/ppc/...Joel Brobecker2-4/+4
... where it belongs.
2013-05-032013-05-03 Hafiz Abid Qadeer <abidh@codesourcery.com>Hafiz Abid Qadeer2-13/+6
revert: 2013-04-19 Nathan Froyd <froydnj@codesourcery.com> * ppc-instructions (isel): New instruction.
2013-04-192013-04-19 Nathan Froyd <froydnj@codesourcery.com>Hafiz Abid Qadeer2-0/+17
* ppc-instructions (isel): New instruction.
2013-03-31sim: frv/m32r: back out hard failure when dv-sockser is not availableMike Frysinger9-42/+34
These sims have optional support for the dv-sockser model, so do not make them hard failures. The Makefile made it seem like they didn't actually support things dynamically, but a further code dive into the source and the Makefile shows that things work out.
2013-03-26sim: rewrite SIM_AC_OPTION_HARDWARE a bit to simplify thingsMike Frysinger23-354/+448
There's no need to put the majority of the logic into the 3rd arg of the AC_ARG_ENABLE. Coupled with the lack of indentation, it makes it hard to follow, error prone to update, and duplicates code (with the 4th arg). So pull the logic out of the 3rd arg and outside of the AC_ARG_ENABLE macro. This allows us to gut the 4th arg entirely, merge with the code that followed the macro, and fix bugs related to the new dv-sockser in the process. Hopefully building the various sims with the default sim-hardware settings, as well as with explicit --{dis,en}able-sim-hardware flags, should all just work now.
2013-03-232013-03-23 Joel Sherrill <joel.sherrill@oarcorp.com>Joel Sherrill5-29/+34
* configure.ac: Use $SIM_DV_SOCKSER_O. * configure: Regenerated.
2013-03-232013-03-23 Joel Sherrill <joel.sherrill@oarcorp.com>Joel Sherrill12-8/+590
* configure.ac: Fail if dv-sockser.o not available. Error when --disable-sim-hardware is specified. * configure: Regenerated.
2013-03-232013-03-23 Joel Sherrill <joel.sherrill@oarcorp.com>Joel Sherrill5-3/+175
* configure.ac: Fail if dv-sockser.o not available. Error when --disable-sim-hardware is specified. * tconfig.in: Conditionalize use of dv_sockser_install. * configure: Regenerated. * config.in: Regenerated.
2013-03-232013-03-23 Joel Sherrill <joel.sherrill@oarcorp.com>Joel Sherrill5-6/+60
* configure.ac: Address use of dv-sockser.o. * tconfig.in: Conditionalize use of dv_sockser_install. * configure: Regenerated. * config.in: Regenerated.
2013-03-232013-03-23 Joel Sherrill <joel.sherrill@oarcorp.com>Joel Sherrill2-2/+23
* acinclude.m4: Add SIM_DV_SOCKSER_O which is empty on hosts which do not support dv-sockser.o. Add always as option to first argument to SIM_AC_OPTION_HARDWARE. Fail if hardware is always required to be enabled by simulator.
2013-03-15gdb:Steve Ellcey12-11/+25
2013-03-15 Steve Ellcey <sellcey@mips.com> * remote-sim.c (sim_command_completer): Make char arguments const. include: 2013-03-15 Steve Ellcey <sellcey@mips.com> * gdb/remote-sim.h (sim_command_completer): Make char arguments const. sim: 2013-03-15 Steve Ellcey <sellcey@mips.com> * arm/wrapper.c (sim_complete_command): Make char arguments const. * avr/interp.c (sim_complete_command): Ditto. * common/sim-options.c (sim_complete_command): Ditto. * cr16/interp.c (sim_complete_command): Ditto. * erc32/interf.c (sim_complete_command): Ditto. * m32c/gdb-if.c (sim_complete_command): Ditto. * microblaze/interp.c (sim_complete_command): Ditto. * ppc/sim_calls.c (sim_complete_command): Ditto. * rl78/gdb-if.c (sim_complete_command): Ditto. * rx/gdb-if.c (sim_complete_command): Ditto. * sh/interp.c (sim_complete_command): Ditto.
2013-03-14Fix erc32 simulator out-of-tree build failure.Joel Brobecker2-1/+6
sim/erc32/ChangeLog: * Makefile.in: Include build directory in search path to find config.h
2013-01-28 * simops.c (v850_rotl): New function.Nick Clifton6-0/+278
(v850_bins): New function. * simops.h: Add prototypes fir v850_rotl and v850_bins. * v850-dc: Add entries for V850e3v5. * v850.igen: Add support for v850e3v5. (ld.dw, st.dw, rotl, bins): New patterns.
2013-01-17Remove debug outputAnthony Green2-1/+4
2013-01-16 * rx.c (decode_opcode): Handle RXO_satr.Nick Clifton2-0/+20
2013-01-10 * interp.c (sim_open): Add support for bfd_arch_v850_rh850Nick Clifton4-16/+121
architecture type. Add support for bfd_mach_v850e2 and bfd_mach_v850e2v3 machine numbers. * v850.igen (dbtrap): Add support for SIM_OPEN_DEBUG. (cmpf.d): Correct order of operands. (cmpf.s): Likewise. (trncf.dul): New pattern. (trncf.duw): New pattern. (trncf.sul): New pattern. (trncf.suw): New pattern. * v850-dc: Correct bitfield selection for TRNCF.SW and CVTF.SW.
2013-01-08 * mem.c (MDBL): Correct value.Nick Clifton2-2/+7
(MDBH): Correct value.
2013-01-01Update years in copyright notice for the GDB files.Joel Brobecker539-585/+542
Two modifications: 1. The addition of 2013 to the copyright year range for every file; 2. The use of a single year range, instead of potentially multiple year ranges, as approved by the FSF.
2012-12-20Revert GPL version change in sim/bfin/aclocal.m4Joel Brobecker2-1/+7
sim/bfin/ChangeLog: * aclocal.m4: Revert the previous change changing the license from GPL v2 or later to GPL v3 or later (this file was generated).
2012-12-20Revert GPL version change in linux-fixed-code.s.Joel Brobecker2-1/+6
sim/bfin/ChangeLog: * linux-fixed-code.s: Revert the previous change changing the license from GPL v2 or later to GPL v3 or later.
2012-12-19Update sim's COPYING files.Joel Brobecker4-580/+1256
sim/arm/ChangeLog: * COPYING: Update to GPL version 3. sim/ppc/ChangeLog: * COPYING: Update to GPL version 3.
2012-12-19[sim] Update old contact info in GPL license noticesJoel Brobecker256-523/+264
sim/ChangeLog: Update old contact info in GPL license notices.
2012-12-19Update sim copyright headers from GPLv2-or-later to GPLv3-or-later.Joel Brobecker169-170/+174
gdb/sim/ChangeLog: Update the non-FSF-copyrighted files in sim to GPLv3 or later.
2012-11-20Fix sim build when configured with --enable-pluginsH.J. Lu31-27/+225583
* common/Make-common.in: Use lt_cv_dlopen_libs under PLUGINS condition. * common/acinclude.m4: Define lt_cv_dlopen_libs. * arm/configure: Regenerate. * avr/configure: Regenerate. * bfin/configure: Regenerate. * common/configure: Regenerate. * cr16/configure: Regenerate. * cris/configure: Regenerate. * d10v/configure: Regenerate. * erc32/configure: Regenerate. * frv/configure: Regenerate. * h8300/configure: Regenerate. * igen/configure: Regenerate. * iq2000/configure: Regenerate. * lm32/configure: Regenerate. * m32c/configure: Regenerate. * m32r/configure: Regenerate. * m68hc11/configure: Regenerate. * mcore/configure: Regenerate. * microblaze/configure: Regenerate. * mips/configure: Regenerate. * mn10300/configure: Regenerate. * moxie/configure: Regenerate. * ppc/configure: Regenerate. * rl78/configure: Regenerate. * rx/configure: Regenerate. * sh/configure: Regenerate. * sh64/configure: Regenerate. * testsuite/configure: Regenerate. * v850/configure: Regenerate.
2012-11-05* MAINTAINERS: Update my email address.Stephane Carrez2-1/+5
2012-10-032012-10-04 Chao-ying Fu <fu@mips.com>Steve Ellcey2-0/+16
Steve Ellcey <sellcey@mips.com> * mips/mips3264r2.igen (rdhwr): New.
2012-09-24Forgot to include ChangeLog in last checkin.Steve Ellcey1-0/+6
2012-09-242012-09-24 Steve Ellcey <sellcey@mips.com>Steve Ellcey3-3/+11
* mips/basic.exp: Add mips*-mti-elf* target. * configure.ac: Add mips*-mti-elf* target. * configure: Regenerate.
2012-09-13 * v850.igen (W,WWWW): Correct computation of register number.Nick Clifton2-14/+19
(JR32): Remove unnecessary comma. (cmovf.s): Register 0 is an invalid source register. (maddf.s): Remove bogus intermediary rounding. (nmaddf.s): Likewise. (trncf.sl): Remove bogus initial rounding. (trncf.dw): Likewise. (trncf.sl): Likewise. (trncf.sw): Likewise.
2012-09-08Adjust for branch target encoding changeAnthony Green2-10/+15
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