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AgeCommit message (Expand)AuthorFilesLines
2022-12-21sim: bpf: invert sim_cpu storageMike Frysinger3-7/+13
2022-12-21sim: cgen: prep for inverting sim_cpu storageMike Frysinger2-0/+15
2022-12-21sim: riscv: invert sim_cpu storageMike Frysinger3-191/+258
2022-12-21sim: pru: invert sim_cpu storageMike Frysinger3-8/+31
2022-12-21sim: example-synacor: invert sim_cpu storageMike Frysinger3-37/+47
2022-12-21sim: h8300: invert sim_cpu storageMike Frysinger2-34/+36
2022-12-21sim: m68hc11: invert sim_cpu storageMike Frysinger10-354/+446
2022-12-21sim: mips: invert sim_cpu storageMike Frysinger2-73/+90
2022-12-21sim: v850: invert sim_cpu storageMike Frysinger3-20/+23
2022-12-21sim: mcore: invert sim_cpu storageMike Frysinger2-27/+41
2022-12-21sim: aarch64: invert sim_cpu storageMike Frysinger5-108/+152
2022-12-21sim: microblaze: invert sim_cpu storageMike Frysinger3-8/+8
2022-12-21sim: avr: invert sim_cpu storageMike Frysinger2-99/+108
2022-12-21sim: moxie: invert sim_cpu storageMike Frysinger2-14/+13
2022-12-21sim: msp430: invert sim_cpu storageMike Frysinger3-120/+106
2022-12-21sim: ft32: invert sim_cpu storageMike Frysinger3-95/+99
2022-12-21sim: bfin: invert sim_cpu storageMike Frysinger2-10/+5
2022-12-20sim: sim_cpu: invert sim_cpu storageMike Frysinger7-39/+45
2022-12-20sim: move register headers into sim/ namespace [PR sim/29869]Mike Frysinger16-16/+16
2022-12-20sim: ppc: drop old dgen.c generatorMike Frysinger3-363/+6
2022-12-20sim: ppc: move spreg.[ch] files to the source treeMike Frysinger5-0/+1608
2022-12-19sim: ppc: change spreg switch table generation to compile-timeMike Frysinger4-15/+16
2022-12-19sim: dv-core: add hw_detach_address method [PR sim/25211]Mike Frysinger2-13/+18
2022-11-12sim: pru: Fix behaviour when loop count is zeroDimitar Dimitrov2-2/+43
2022-11-11sim: igen: cleanup archaic pointer-to-long printf castsMike Frysinger4-53/+49
2022-11-11sim: v850: rename v850.dc to align with other portsMike Frysinger3-2/+2
2022-11-11sim: igen: fix hang when decoding boolean rule constantsMike Frysinger1-0/+2
2022-11-11sim: igen: mark error func as noreturn since it exitsMike Frysinger1-1/+1
2022-11-11sim: igen: mark output funcs with printf attributeMike Frysinger2-7/+4
2022-11-11sim: igen: constify various func argumentsMike Frysinger31-265/+380
2022-11-11sim: ppc: rename ppc-instructions to powerpc.igenMike Frysinger4-6/+6
2022-11-10sim: ppc: drop old makefile fragmentMike Frysinger1-3/+0
2022-11-10sim: ppc: drop support for dgen -L optionMike Frysinger1-5/+1
2022-11-10sim: ppc: collapse is_readonly & length switch tables heavilyMike Frysinger1-7/+15
2022-11-10sim: ppc: collapse is_valid switch table moreMike Frysinger1-1/+4
2022-11-10sim: ppc: pull default switch return outMike Frysinger1-2/+1
2022-11-10sim: ppc: constify spreg tableMike Frysinger1-2/+2
2022-11-10sim: igen: add missing newline to various error messagesMike Frysinger5-6/+6
2022-11-10sim: restore lstat & mkdir func checksMike Frysinger3-2/+16
2022-11-10sim: ppc: drop obsolete USE_WIN32API checkMike Frysinger4-27/+0
2022-11-09sim: ppc: add missing parens with e500 macroMike Frysinger1-16/+16
2022-11-09sim: ppc: drop useless linking of helper toolsMike Frysinger1-1/+1
2022-11-08sim: mips: call Unpredictable instead of setting bogus values [PR sim/29276]Mike Frysinger1-2/+2
2022-11-07sim: riscv: add missing AC_MSG_RESULT callMike Frysinger2-0/+3
2022-11-07sim: v850: drop subdir configure logicMike Frysinger7-2962/+27
2022-11-07sim: mn10300: drop subdir configure logicMike Frysinger7-2969/+34
2022-11-07sim: or1k: drop subdir configure logicMike Frysinger7-2966/+32
2022-11-07sim: bpf: drop subdir configure logicMike Frysinger7-2979/+44
2022-11-07sim: riscv: drop subdir configure logicMike Frysinger8-3138/+65
2022-11-07sim: .gdbinit: generate for all arch subdirsMike Frysinger3-143/+180
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