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1997-09-23Remove need to update <targ>/Makefile.in when adding optional optionsAndrew Cagney26-585/+1859
to <targ>/configure.in. Simplify logic used to select target [default] endianness.
1997-09-22Add memory alignment config option.Andrew Cagney6-87/+204
1997-09-22Enable --alignment option, stop sim-options.c hardwiring the alignment.Andrew Cagney4-3/+8
1997-09-22Fix disabling of model code when simulator does not support modeling.Andrew Cagney2-2/+24
Stops `-p' crashing simulators.
1997-09-22Simplify logic behind the generic configuration option --enable-sim-alignment.Andrew Cagney15-50/+145
1997-09-22Add support for --enable-sim-alignment to simulator common aclocal.m4Andrew Cagney17-80/+311
Add support for --alignment={strict,nonstrict,forced} to simulator common run-time options. For v850 use, make the default NONSTRICT_ALIGNMENT.
1997-09-20Removed the v850eq sanitizationNick Clifton3-72/+7
1997-09-20Add handling for 3900's SDBBP, DERET, and RFE insns.Gavin Romig-Koch2-7/+15
* gencode.c (SDBBP,DERET): Added (3900) insns. (RFE): Turn on for 3900. * interp.c (DebugBreakPoint,DEPC,Debug,Debug_*): Added. (dsstate): Made global. (SUBTARGET_R3900): Added. (CANCELDELAYSLOT): New. (SignalException): Ignore SystemCall rather than ignore and terminate. Add DebugBreakPoint handling. (decode_coproc): New insns RFE, DERET; and new registers Debug and DEPC protected by SUBTARGET_R3900. (sim_engine_run): Use CANCELDELAYSLOT rather than clearing bits explicitly. * Makefile.in,configure.in: Add mips subtarget option. * configure: Update.
1997-09-19 * gencode.c: Add r3900 (tx39).Gavin Romig-Koch2-21/+40
* gencode.c: Fix some configuration problems by improving the relationship between tx19 and tx39.
1997-09-19Add alignment option.Andrew Cagney1-0/+1
Add support for hardwired and default alignment to configuration.
1997-09-19More tests.Andrew Cagney9-16/+255
Have sld check verify that the processor is a v850eq.
1997-09-19Clean up tracing for Bcond & jmp insns.Andrew Cagney4-369/+162
Fix computation of disp16 and disp22. Clean up tracing of sld* insns.
1997-09-19Correctly locate `_' in generated names.Andrew Cagney1-1/+1
1997-09-19Fix cmov immed.Andrew Cagney4-34/+77
1997-09-19Change semantic function name to semantic_<INSN>_<FMT> instead ofAndrew Cagney2-3/+8
semantic_<FMT>_<INSN>.
1997-09-19Fix cmov insn.Andrew Cagney4-17/+30
1997-09-18sanitization fixes. typoes, missing fences, "start" instead of "end", etc.Felix Lee1-8/+2
1997-09-18add missing files.Felix Lee4-1/+44
1997-09-18v850 files that weren't being removed if !keep-v850Felix Lee2-2/+6
1997-09-17 * sim-main.h (kill): macro was missing args.Felix Lee2-1/+10
(SIGTRAP): define for MSVC.
1997-09-17Test US bit of v850eq.Andrew Cagney3-0/+65
Loop program for testing interrupt delivery.
1997-09-17Clean up more tracing.Andrew Cagney5-211/+112
FIX interrupt delivery - was zapping PSW before it had been saved. FIX interrupt return, was one instruction out.
1997-09-17* sim-events.c (ETRACE): Use trace_printf not sim_io_printf forAndrew Cagney1-0/+10
trace output. * sim-core.c (sim_core_signal): When bad access halt simulator SIGSEGV / SIGBUS instead of aborting. (signal.h): Include. * sim-watch.c (sim_watchpoint_install): Handler for watchpoint options was missing.
1997-09-17Fix tracing for: "ctret", "bsw", "hsw"Andrew Cagney4-144/+140
Fix bugs in: "bsh", "callt", "stsr".
1997-09-17Define MOVED macro, move sub-bitfield from XXX to YYY.Andrew Cagney1-0/+4
1997-09-17More v850 simulator tests.Andrew Cagney8-8/+62
1997-09-17More v850 simulator tests.Andrew Cagney12-23/+1114
1997-09-17Add/test 8bit bit manipuation macros.Andrew Cagney2-32/+71
Test LS and MS versions of SEXT macro. Simplify/test macro returning a single bit.
1997-09-16Generic rules for building simple simulator test programs.Andrew Cagney1-0/+48
1997-09-16 * sim/mips/gencode.c (build_instruction): Don't need to subtract 4 forGavin Romig-Koch2-1/+7
JALR, just 2.
1997-09-16 * sim/mips/interp.c: Correct some HASFPU problems.Gavin Romig-Koch2-5/+19
1997-09-16Smooth some of ALU tracing's rough edges.Andrew Cagney5-277/+292
Fix switch insn.
1997-09-16More sim-bits testing.Andrew Cagney2-4/+37
1997-09-16Add {LS,MS}SEXT and {LS,MS}INSERTED macros. Eliminates bug in SEXT.Andrew Cagney3-25/+107
1997-09-16Use trace_one_insn in trace functions. Buffer up trace data so thatAndrew Cagney3-164/+133
it is displayed in a single block.
1997-09-16v850eq simulator tests.Andrew Cagney6-0/+132
1997-09-16Restrict ldsr (load system register) to modifying just non-reserved PSW bits.Andrew Cagney5-59/+55
For v850eq, include PSW[US] in bits that can be modified.
1997-09-16Add v850e version of breakpoint instruction.Andrew Cagney4-5/+34
1997-09-16Differentiate between a non-zero string and a constant zero field.Andrew Cagney1-0/+5
1997-09-16 * simops.c (Multiply64): Don't store into register zero.Jim Wilson2-2/+11
1997-09-15For instructions moved into v850.igen was computing (wrong) NIA whenAndrew Cagney4-14/+28
this wasn't needed.
1997-09-15 * igen.c (gen_run_c): Handle non-multi-sim case.Andrew Cagney2-22/+36
1997-09-15Fix sanitization for v850 V v850e V v850eqAndrew Cagney5-429/+506
1997-09-15Update to reflect change to sim/common/aclocal.m4 (allow sim/commonAndrew Cagney9-26/+55
directory to specify its own unqiue config.h file).
1997-09-15For v850eq start up with US bit set.Andrew Cagney6-333/+244
Let sim_analyze_program determine the architecture. Fix various sanitizations.
1997-09-15Determine ARCHITECTURE from program if possible.Andrew Cagney2-2/+14
Rename common's generated config.h to cconfig.h.
1997-09-15 * callback.c (os_write): divert stdout and stderr to theirAndrew Cagney1-0/+5
respective hooks.
1997-09-12Check reserved bits before executing instructions.Andrew Cagney7-43/+144
Make v850[eq] the the default simulator. Report illegal instructions. Include v850e instructions in v850eq.
1997-09-12v850eq wasn't building igen directory.Andrew Cagney3-0/+9
1997-09-12Add profiling support to v850*.Andrew Cagney6-16/+83
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