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1997-06-12 * simops.c: Fix thinko in last change.Jeff Law2-1/+5
1997-06-10 * simops.c: "call" stores the callee saved registers into theJeff Law2-53/+55
stack! Update the stack pointer properly when done with register saves.
1997-06-10 * simops.c: Fix return address computation for "call" instructions.Jeff Law2-2/+10
1997-06-06Open in binary mode when available.Andrew Cagney1-0/+8
1997-06-06Clean up formatting of instruction traces.Andrew Cagney1-0/+33
1997-06-05Verify magic number of simulator struct.Andrew Cagney1-0/+4
1997-06-04Initialize the sim-engine module.Andrew Cagney1-0/+12
1997-06-03o Fixes to repeated watchpointsAndrew Cagney3-110/+228
o Add mips ISA instructions needed to handle interrupts
1997-06-02o Fix padd insnAndrew Cagney1-8/+12
o Take an interrupt when an int event occures.
1997-05-30Add assembler information to igen input files.Andrew Cagney7-153/+309
1997-05-29Fix subu immed - was incorrectly using unsigned.Andrew Cagney3-1/+10
1997-05-29Add a simple dissasembler to igenAndrew Cagney4-38/+740
1997-05-27Fix watching PC for 64bit (mips) target.Andrew Cagney2-42/+146
Stop watchpoints corrupting the event queue.
1997-05-27Extend xor-endian and per-cpu support in core module.Andrew Cagney11-63/+294
Allow negated test when watching value within core.
1997-05-23Preliminary suport for xor-endian suport in core module.Andrew Cagney6-79/+181
1997-05-23Incorrect test for zero-r0 code gen.Andrew Cagney2-2/+12
1997-05-23Enumerate longjmp's return type.Andrew Cagney1-0/+5
1997-05-22ifdef out uses of simSTOP, simSTEP and simBE when DEBUG is defined.Gavin Romig-Koch2-0/+9
1997-05-22Change longjmp param/setjmp return value used for simulator restart from 0 to 2.Gavin Romig-Koch3-6/+27
1997-05-22 * interp.c (sim_resume): Add missing case in big switchJeff Law2-0/+6
statement (for extb instruction).
1997-05-21Watchpoint interface.Andrew Cagney16-817/+1486
1997-05-20 * interp.c: Replace all references to load_mem and store_memJeff Law3-340/+295
with references to load_byte, load_half, load_3_byte, load_word and store_byte, store_half, store_3_byte, store_word. (INLINE): Delete definition. (load_mem_big): Likewise. (max_mem): Make it global. (dispatch): Make this function inline. (load_mem, store_mem): Delete functions. * mn10300_sim.h (INLINE): Define. (RLW): Delete unused definition. (load_mem, store_mem): Delete declarations. (load_mem_big): New definition. (load_byte, load_half, load_3_byte, load_word): New functions. (store_byte, store_half, store_3_byte, store_word): New functions. * simops.c: Replace all references to load_mem and store_mem with references to load_byte, load_half, load_3_byte, load_word and store_byte, store_half, store_3_byte, store_word.
1997-05-20Part II of adding callback argument to sim_open(). Update all theAndrew Cagney7-56/+48
other simulators; remove SIM_DESC from depreciated function sim_set_callbacks().
1997-05-20Depreciate sim_set_callbacks() function. Set simulator callbacksAndrew Cagney3-18/+19
during sim_open().
1997-05-19Make getpid, kill supported system callsMichael Meissner6-39/+157
1997-05-19 * interp.c (dispatch): Make this an inline function.Jeff Law3-7/+10
* simops.c (syscall): Use callback->write regardless of what file descriptor we're writing too.
1997-05-19Graft sim/common event and other code onto the mips simulator.Andrew Cagney5-220/+196
1997-05-19Update.Andrew Cagney1-3/+8
1997-05-19Make simulator event-queue manager a bit more signal safe.Andrew Cagney3-0/+26
1997-05-19o Implement generic halt/restart/abort module.Andrew Cagney18-368/+1406
Use in tic80 and d30v simulators. o Add signal hook to sim-core module
1997-05-19Pacify gcc.Andrew Cagney1-0/+4
1997-05-18 * interp.c (load_mem_big): Remove function. It's now a macroJeff Law2-26/+34
defined elsewhere. (compare_simops): New function. (sim_open): Sort the Simops table before inserting entries into the hash table. * mn10300_sim.h: Remove unused #defines. (load_mem_big): Define. Another 20% so performance improvement for the mn10300 simulator.
1997-05-17Treat infinities like normal numbers for purposes of comparisonsMichael Meissner2-6/+11
1997-05-16 * callback.c (os_close): Mark the descriptor as beingJeff Law2-6/+127
available if the close succeeded. (os_open): Pass 0644 as the mode of the file being created. Bring Bob's changes over from the mec branch.
1997-05-16 * interp.c (load_mem): If we get a load from an out of rangeJeff Law2-0/+18
address, abort. (store_mem): Likewise for stores. (max_mem): New variable.
1997-05-16o Make tic80 insn file more `cache ready'Andrew Cagney9-174/+218
o Have igen always zero r0 instead of constantly checking if the designated register is r0.
1997-05-15Remove some of the flake from the c80 floating point.Andrew Cagney5-50/+617
1997-05-15More floating point operations.Andrew Cagney3-21/+137
1997-05-15Fix double conversion problem.Andrew Cagney4-45/+76
1997-05-15Passify gcc's warnings.Andrew Cagney2-1/+5
1997-05-14Make columns line up for fpu operation tracingMichael Meissner2-7/+13
1997-05-13Make sure r0 == 0; Return EINVAL for system calls that are defined but not ↵Michael Meissner3-0/+37
provided; Provide traps 74-79 as debugging traps
1997-05-13Remove ANNULed cycle - was confusing gdb.Andrew Cagney4-56/+54
1997-05-12Fix ld/st tracingMichael Meissner2-2/+6
1997-05-12Clear cntrl-c after handling it.Andrew Cagney3-2/+8
1997-05-12c80 simulator fixes.Andrew Cagney10-70/+242
1997-05-12Match commands like `(gdb) sim a b c' against options --a-b-c.Andrew Cagney1-0/+8
1997-05-12Fix endian problems with ld.d/st.dMichael Meissner2-2/+9
1997-05-11Fix shift/lmo insns; Subu does arithmetic unsignedMichael Meissner4-24/+88
1997-05-10And short immediate instructions use unsigned immediates, not signed.Michael Meissner2-4/+9
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