Age | Commit message (Collapse) | Author | Files | Lines |
|
Committed by Andrew Cagney.
* mloopx.in: Update copyright.
(xextract-pbb): Fixed trap for system calls operation in parallel.
* mloop2.in (xextract-pbb): Ditto.
|
|
* gencode.c: (op tab): Some refs and defs fixes.
"fsrra" -> "fsrra <FREG_N>".
"sleep": replace array ref with array addr.
"trapa": ditto.
|
|
* gencode.c: Comment and whitespace clean-ups.
|
|
* ppc-instructions: Update copyright.
(convert_to_integer): Add trailing ";" to label.
|
|
2004-01-26 Chris Demetriou <cgd@broadcom.com>
* configure.in (mips*-*-*): Configure in testsuite.
* configure: Regenerate.
[ sim/testsuite/ChangeLog ]
2004-01-26 Chris Demetriou <cgd@broadcom.com>
* sim/mips: New directory. Tests for the MIPS simulator.
[ sim/testsuite/sim/mips/ChangeLog ]
2004-01-26 Chris Demetriou <cgd@broadcom.com>
* basic.exp: New file.
* testutils.inc: New file.
* sanity.s: New file.
|
|
test passes.
|
|
* mips.igen (check_mf_cycles, check_mt_hilo, check_mf_hilo)
(check_mult_hilo): Improve comments.
(check_div_hilo): Likewise. Also, fork off a new version
to handle mips32/mips64 (since there are no hazards to check
in MIPS32/MIPS64).
|
|
|
|
|
|
* gencode.c: Whitespace cleanup.
* interp.c: Ditto.
|
|
* dmxy.s, fipr.s, fpchg.s, ldrc.s, loop.s, movli.s, movua.s,
movxy.s, pabs.s, pclr.s, prnd.s, psub.s, pswap.s: New files.
* allinsn.exp: Add new tests.
* testutils.inc (set_sr_bit): Add argument.
(set_greg): Add .align directives.
|
|
* gencode.c: Replace 'Hitachi' with 'Renesas'.
(op tab): Add new instructions for sh4a, DBR, SBR.
(expand_opcode): Add handling for new movxy combinations.
(gensym_caselist): Ditto.
(expand_ppi_movxy): Remove movx/movy expansions,
now handled in expand_opcode.
(gensym): Add some helpful macros.
(expand_ppi_code): Flatten loop for simplicity, tweak for 12-bit
instead of 8-bit table (some insns are ambiguous to 8 bits).
(ppi_gensim, main): Generate 12-bit instead of 8-bit ppi table.
* interp.c: Replace 'Hitachi' with 'Renesas'.
(union saved_state_type): Add dbr, sgr, ldst.
(get_loop_bounds_ext): New function.
(init_dsp): Add bfd_mach_sh4al_dsp.
(sim_resume): Handle extended loop bounds.
|
|
* gencode.c (expand_opcode): Simplify and reorganize.
Eliminate "shift" parameter. Eliminate "4 bits at a time"
assumption. Flatten switch statement to a single level.
Add "eeee" token for even-numbered registers.
(bton): Delete.
(fsca): Use "eeee" token.
(ppi_moves): Rename to "expand_ppi_movxy". Do the ddt
[movx/movy] expansion here, as well as the ppi expansion.
(gensim_caselist): Accept 'eeee' along with 'nnnn'.
|
|
* compile.c (sim_load): Don't pass a type to bfd_openr.
|
|
(O_RDONLY): Do not define.
(O_WRONLY): Likewise.
(O_RDWR): Likewise.
(targ-vals.h): Include it.
(translate_open_mode): Use TARGET_O_* instead of O_*.
(SWIopen): Likewise.
* Makefile.in (armos.o): Depend on targ-vals.h.
|
|
|
|
Patch submitted by Anil Paranjape <AnilP1@KPITCummins.com>
* sim-main.h (H8300H_MSIZE): Increase from 18 bits to 24 bits.
|
|
|
|
|
|
|
|
|
|
|
|
* Makefile.in : Add new machine m32r2.
* m32r2.c : New file for m32r2.
* mloop2.in : Ditto
* model2.c : Ditto
* sem2-switch.c : Ditto
* m32r-sim.h : Add EVB register.
* sim-if.h : Ditto
* sim-main.h : Ditto
* traps.c : Ditto
|
|
(SPR_REGNUM_MAX): Delete.
* frv.c (gdb/sim-frv.h): Include.
(frvbf_fetch_register, frvbf_store_register): Use register number
constants from gdb/sim-frv.h. Check availability of general
purpose and float registers.
|
|
variants.
|
|
|
|
* cache.c (address_interference): Check for higher priority requests
in the same pipeline.
|
|
* gencode.c (tab): Add entries for fsca and fsrra.
(expand_opcode): Allow variable length n / m fields.
|
|
|
|
|
|
* frv-sim.h (REGNUM_LR): Removed.
(REGNUM_SPR_MIN,REGNUM_SPR_MAX): New macros.
* frv.c (frvbf_fetch_register): Fetch SPR registers based on
REGNUM_SPR_MIN and REGNUM_SPR_MAX. Check whether SPRs are implemented.
Return 0 for an unimplemented register. Return the length of the data
for an implemented register.
(frvbf_store_register): Ditto.
|
|
2003-10-30 Andrew Cagney <cagney@redhat.com>
* traps.c: Replace "struct symbol_cache_entry" with "struct
bfd_symbol".
Index: sim/d10v/ChangeLog
2003-10-30 Andrew Cagney <cagney@redhat.com>
* simops.c: Replace "struct symbol_cache_entry" with "struct
bfd_symbol".
Index: sim/common/ChangeLog
2003-10-30 Andrew Cagney <cagney@redhat.com>
* sim-trace.c, sim-base.h: Replace "struct symbol_cache_entry"
with "struct bfd_symbol".
Index: ld/ChangeLog
2003-10-30 Andrew Cagney <cagney@redhat.com>
* emultempl/pe.em, pe-dll.c: Replace "struct symbol_cache_entry"
with "struct bfd_symbol".
Index: bfd/ChangeLog
2003-10-30 Andrew Cagney <cagney@redhat.com>
* syms.c: Replace "struct symbol_cache_entry" with "struct
bfd_symbol".
* vms.h, targets.c, section.c, reloc.c, peicode.h: Ditto.
* mipsbsd.c, elf.c, linker.c, elf-bfd.h, ecoff.c: Ditto.
* cpu-z8k.c, cpu-ns32k.c, cpu-h8500.c, bfd.c, bfd-in.h: Ditto.
* bfd-in2.h: Re-generate.
|
|
* callback.c (os_truncate): Call "truncate", and not "stat".
|
|
* targets.c: Replace "struct sec" with "struct bfd_section"
* syms.c, sparclynx.c, section.c, opncls.c: Ditto.
* libcoff-in.h, libbfd-in.h, elfxx-target.h: Ditto.
* elf.c, coffgen.c, bfd.c, bfd-in.h, aoutf1.h: Ditto.
* aout-tic30.c, aout-target.h:
* bfd-in2.h, libcoff.h, libbfd.h: Regenerate.
Index: binutils/ChangeLog
2003-10-19 Andrew Cagney <cagney@redhat.com>
* coffgrok.h (coff_section): Replace 'struct sec" with "struct
bfd_section".
Index: gdb/ChangeLog
2003-10-19 Andrew Cagney <cagney@redhat.com>
* symtab.c: Replace "struct sec" with "struct bfd_section".
* objfiles.c, linespec.c, blockframe.c, block.c: Ditto.
Index: ld/ChangeLog
2003-10-19 Andrew Cagney <cagney@redhat.com>
* pe-dll.c: Replace "struct sec" with "struct bfd_section".
Index: sim/common/ChangeLog
2003-10-19 Andrew Cagney <cagney@redhat.com>
* sim-base.h: Replace "struct sec" with "struct bfd_section".
|
|
* h8300/compile.c : Addition of extern variable h8300_normal_mode
(SP) : Handle normal mode
(bitfrom) : Use normal mode flag to return suitable value
(lvalue) : Use normal mode flag to return command line location
(decode) : Decode instruction correctly for normal mode
(init_pointers) : Initialise memory correctly for normal mode
(sim_resume) : Handle cases for normal mode using h8300_normal_mode flag
(sim_store_register) : Handle 2 byte PC for normal mode
(sim_fetch_register) : Handle 2 byte PC for normal mode
(set_h8300h) : Set normal mode flag as per architechture
(sim_load) : Allocate 64K for normal mode instead of bigger memory
|
|
* emul_netbsd.c: Only a comment may follow an #endif.
|
|
* Makefile.in (sim_calls.o): No longer depends on gdb/tm.h.
|
|
* callback.h (struct host_callback_struct): New members ftruncate
and truncate.
gdb:
sim/common:
* callback.c (os_ftruncate, os_truncate): New functions.
(default_callback): Initialize ftruncate and truncate members.
sim/sh:
* syscall.h (SYS_truncate, SYS_ftruncate): Define.
* interp.c (trap): Add support for SYS_ftruncate and SYS_truncate.
|
|
Use bfd_section_size and bfd_get_section_vma.
|
|
* sim/frv/testutils.inc (or_gr_immed): New macro.
* sim/frv/fp_exception-fr550.cgs: Write insns using
unaligned registers into the program in order to
cause the required exceptions.
* sim/frv/fp_exception.cgs: Ditto.
* sim/frv/regalign.cgs: Ditto.
|
|
* cpu.h, sem.c: Regenerate.
|
|
* configure.in: Move frv handling to alphabetically correct placement.
|
|
* sim/frv/fr550: New subdirectory.
* sim/frv/fr400/*.cgs: Add fr550 as appropriate.
* sim/frv/fr500/*.cgs: Add fr550 as appropriate.
* sim/frv/interrupts/*.cgs: Add fr550 as appropriate.
* sim/frv/interrupts/*-fr550.cgs: New test cases for fr550.
|
|
* profile-fr550.[ch]: New files.
* configure.in: Move frv handling to alphabetically correct placement.
* Makefile.in: Add fr550 support.
* frv-sim.h,frv.c,interrups.c,memory.c,mloop.in,pipeline.c,
profile.[ch],registers.c,traps.c: Add fr550 support.
* arch.c,arch.h,cpu.c,cpu.h,cpuall.h,model.h,decode.c,decode.h,sem.c:
Regenerate.
|
|
* reset.c (frv_initialize): Call frv_register_control_init first.
|
|
* profile.h (update_FR_ptime): New prototype.
(update_FRdouble_ptime): Ditto.
(update_SPR_ptime): Ditto.
(increase_ACC_busy): Ditto.
(enforce_full_acc_latency): Ditto.
(post_wait_for_SPR): Ditto.
* profile.c (update_FR_ptime): Moved here from profile-fr500.c.
(update_FRdouble_ptime): Ditto.
(update_SPR_ptime): New function.
(increase_ACC_busy): Ditto.
(enforce_full_acc_latency): Ditto.
(vliw_wait_for_fdiv_resource): Correct resource name.
(vliw_wait_for_fsqrt_resource): Ditto.
(post_wait_for_SPR): New function.
* profile-fr500.c (frvbf_model_fr500_u_commit): New function.
(frvbf_model_fr500_u_gr2fr): Pass out_FRk as output register to
adjust_float_register_busy.
(frvbf_model_fr500_u_gr_load): Record latency of SPR registers.
(frvbf_model_fr500_u_fr_load): Wait for and record latency of SPR
registers.
(frvbf_model_fr500_u_float_arith): Ditto.
(frvbf_model_fr500_u_float_dual_arith): Ditto.
(frvbf_model_fr500_u_float_div): Ditto.
(frvbf_model_fr500_u_float_sqrt): Ditto.
(frvbf_model_fr500_u_float_convert): Ditto.
(update_FR_ptime): Moved to profile.c
(update_FRdouble_ptime): Moved to profile.c
* profile-fr400.c (update_FR_ptime): Removed. Identical to functions
for other machines.
(update_FRdouble_ptime): Ditto.
* arch.h,cpu.h,sem.c,decode.[ch],model.c,sem.c: Regenerated.
|
|
* sim/frv/nldqi.cgs: Remove. This insn was never implemented
by Fujitsu.
|
|
* sim/frv/rstqf.cgs: Use nldq instead of nldqi.
* sim/frv/rstq.cgs: Use nldq instead of nldqi.
|
|
|
|
* registers.c (frv_check_spr_read_access): Check for access to
ACC4-ACC63 and ACCG4-ACCG63.
* profile.h (frv-desc.h): #include it.
(spr_busy): New member of FRV_PROFILE_STATE.
(spr_latency): Ditto.
(GNER_FOR_GR): New macro.
(FNER_FOR_FR): New maccro.
(update_SPR_latency): New function.
(vliw_wait_for_SPR): New function.
* profile.c (profile-fr550.h): #include it.
(update_latencies): Update SPR latencies.
(update_target_latencies): Ditto.
(update_SPR_latency): New function.
(vliw_wait_for_SPR): New function.
* profile-fr500.c (frvbf_model_fr500_u_idiv): Record GNER latency.
(frvbf_model_fr500_u_trap): Removed unused variable, ps.
(frvbf_model_fr500_u_check): Ditto.
(frvbf_model_fr500_u_clrgr): New unit modeller for fr500.
(frvbf_model_fr500_u_clrfr): Ditto.
(frvbf_model_fr500_u_spr2gr): Wait for SPR.
(frvbf_model_fr500_u_gr2spr): Ditto.
* frv-sim.h (H_SPR_ACC4): New macro.
(H_SPR_ACCG4): New macro;
(H_SPR_ACC0): Removed.
(H_SPR_ACCG0): Removed.
* arch.h,model.c,sem[ch],decode.[ch]: Regenerated.
|