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2012-06-06Move config.h to start of includes.Michael Eager1-1/+1
2012-06-06Add #include "config.h".Michael Eager2-0/+5
2012-05-242012-05-24 Pedro Alves <palves@redhat.com>Pedro Alves4-3/+11
* sim-signal.h (sim_signal_to_target): Rename to ... (sim_signal_to_gdb_signal): ... this. * sim-signal.c (sim_signal_to_target): Rename to ... (sim_signal_to_gdb_signal): ... this. * sim-reason.c (sim_stop_reason): Adjust to rename.
2012-05-24gdb/Pedro Alves21-51/+111
2012-05-24 Pedro Alves <palves@redhat.com> PR gdb/7205 Replace TARGET_SIGNAL_ with GDB_SIGNAL_ throughout. gdb/gdbserver/ 2012-05-24 Pedro Alves <palves@redhat.com> PR gdb/7205 Replace TARGET_SIGNAL_ with GDB_SIGNAL_ throughout. include/gdb/ 2012-05-24 Pedro Alves <palves@redhat.com> PR gdb/7205 * gdb/signals.def: Replace TARGET_SIGNAL_ with GDB_SIGNAL_ throughout. sim/arm/ 2012-05-24 Pedro Alves <palves@redhat.com> PR gdb/7205 Replace TARGET_SIGNAL_ with GDB_SIGNAL_ throughout. sim/avr/ 2012-05-24 Pedro Alves <palves@redhat.com> PR gdb/7205 Replace TARGET_SIGNAL_ with GDB_SIGNAL_ throughout. sim/common/ 2012-05-24 Pedro Alves <palves@redhat.com> PR gdb/7205 Replace TARGET_SIGNAL_ with GDB_SIGNAL_ throughout. sim/cr16/ 2012-05-24 Pedro Alves <palves@redhat.com> PR gdb/7205 Replace TARGET_SIGNAL_ with GDB_SIGNAL_ throughout. sim/d10v/ 2012-05-24 Pedro Alves <palves@redhat.com> PR gdb/7205 Replace TARGET_SIGNAL_ with GDB_SIGNAL_ throughout. sim/erc32/ 2012-05-24 Pedro Alves <palves@redhat.com> PR gdb/7205 Replace TARGET_SIGNAL_ with GDB_SIGNAL_ throughout. sim/m32c/ 2012-05-24 Pedro Alves <palves@redhat.com> PR gdb/7205 Replace TARGET_SIGNAL_ with GDB_SIGNAL_ throughout. sim/ppc/ 2012-05-24 Pedro Alves <palves@redhat.com> PR gdb/7205 Replace TARGET_SIGNAL_ with GDB_SIGNAL_ throughout. sim/rl78/ 2012-05-24 Pedro Alves <palves@redhat.com> PR gdb/7205 Replace TARGET_SIGNAL_ with GDB_SIGNAL_ throughout. sim/rx/ 2012-05-24 Pedro Alves <palves@redhat.com> PR gdb/7205 Replace TARGET_SIGNAL_ with GDB_SIGNAL_ throughout.
2012-05-24gdb/Pedro Alves3-2/+8
2012-05-24 Pedro Alves <palves@redhat.com> PR gdb/7205 Replace target_signal with gdb_signal throughout. gdb/gdbserver/ 2012-05-24 Pedro Alves <palves@redhat.com> PR gdb/7205 Replace target_signal with gdb_signal throughout. include/gdb/ 2012-05-24 Pedro Alves <palves@redhat.com> PR gdb/7205 Replace target_signal with gdb_signal throughout. sim/common/ 2012-05-24 Pedro Alves <palves@redhat.com> PR gdb/7205 Replace target_signal with gdb_signal throughout.
2012-05-20 PR 14072Hans-Peter Nilsson2-0/+6
* interp.c: Include config.h before system header files.
2012-05-19 PR 14072Nick Clifton21-4/+56
* wrapper.c: Include config.h before system header files. * callback.c: Include config.h before system header files. * cgen-trace.c: Likewise. * cgen-utils.c: Likewise. * gentmap.c: Likewise. * sim-if.c: Include config.h before system header files. * compile.c: Include config.h before system header files. * sim-main.h: Likewise. * gdb-if.c: Include config.h before system header files. * load.c: Likewise. * syscalls.c: Likewise. * trace.c: Likewise. * interp.c: Include config.h before system header files.
2012-04-09sim: bfin: new PINT modelMike Frysinger7-1/+386
Newer BF54x parts feature an updated GPIO block where all the interrupt handling is split off, so create a new model for the pin interrupts. This is missing the port forwarding aspects, but at least the register interface should be there. Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2012-04-09sim: bfin: new GPIO modelMike Frysinger7-1/+352
Newer BF54x parts feature an updated GPIO block, so create a new model for it. Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2012-04-09sim: bfin: add shift astat testsMike Frysinger4-0/+777
These are randomly generated tests to track down issues in ASTAT handling with shift insns. Signed-off-by: Robin Getz <robin.getz@analog.com> Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2012-04-09sim: bfin: fix ASTAT issues in immediate shiftsMike Frysinger2-17/+64
More ASTAT directed fixes, but this time at the dsp32shift insns. Signed-off-by: Robin Getz <robin.getz@analog.com> Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2012-04-09sim: bfin: fix ASTAT/correctness issues with arithmetic shiftsMike Frysinger2-10/+67
This improves some of the arithmetic shifts to better match the hardware (especially wrt ASTAT behavior). We hit areas where the published documentation is thin so we have to rely on tests run on the hardware to figure out how things should behave. Signed-off-by: Robin Getz <robin.getz@analog.com> Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2012-04-09sim: bfin: more astat testsMike Frysinger3-0/+397
These are the randomly generated tests that directed some of the recent astat related fixes. Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2012-04-09sim: bfin: enable some parallel testsMike Frysinger5-4/+7
Now that we check for valid sub-insns in parallel insns, we can enable the tests that explicitly validate those code paths. Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2012-04-09sim: bfin: more parallel insn checksMike Frysinger2-18/+84
Now that we keep track of the exact parallel insn slot we're in, we can make sure that the current insn being decoded is valid for that slot. This brings us much closer to the hardware in flagging invalid parallel insn combinations. Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2012-04-09sim: bfin: keep track of the exact position of parallel insnsMike Frysinger3-44/+75
Some insns need to know which slot they're in to determine whether they are valid. So add an enum for each slot, and check that rather than the overall insn len. This makes tracking things in the code much clearer. However, this code is functionally the same, so a follow up patch will leverage this more to properly flag invalid parallel insn combos. Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2012-04-09sim: bfin: unify se_all helpers moreMike Frysinger7-54/+64
Now that we have the se_all helpers together and working, we can see what pieces are duplicated in each test and unify them in the common header file. Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2012-04-08sim: bfin: drop excess space in negation insnMike Frysinger2-1/+5
The amod1 helper includes a leading space so it can expand into the empty string when need be, which means the caller need not add spacing itself. Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2012-04-02sim: fix spelling typoMike Frysinger2-1/+5
2012-04-01sim: bfin: throw VEC_ILGAL_I with 32bit insn in group1/group2 slotsMike Frysinger2-0/+8
Parallel insns can only do one 32bit, then two 16bits. So if we see a 2nd 32bit insn after the first 32bit in a parallel insn, abort. Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2012-04-01sim: bfin: simplify field width processing and fix build warningsMike Frysinger2-10/+6
This fix the build time warning: warning: format not a string literal, argument types not checked [-Wformat-nonliteral] Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2012-04-01sim: bfin: fix unused bfrom handling for BF535Mike Frysinger2-1/+5
machs.c: In function 'bfin_model_cpu_init': machs.c:1657:1: warning: 'bfrom' may be used uninitialized in this function [-Wuninitialized] Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2012-04-01sim: bfin: fix build warning/style with auxvt_sizeMike Frysinger2-2/+7
Fix warning about mixing decls and code by moving auxvt_size decl down to the scope where it is used. Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2012-03-31sim: bfin: fix typo in BF54x SIC initMike Frysinger2-1/+5
The current code triggers a warning: dv-bfin_sic.c: In function 'bfin_sic_finish': dv-bfin_sic.c:930:41: warning: operation on 'sic-><U78e8>.bf54x.iwr1' may be undefined [-Wsequence-point] This points out the IWR2 register was not being setup because of a typo. Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2012-03-31sim: bfin: include devices.h to fix build warningsMike Frysinger2-0/+5
The place where these funcs get defined do not include the header that declares their prototypes. Add that to fix -Wmissing-prototypes: devices.c:59:1: warning: no previous prototype for 'dv_bfin_mmr_invalid' devices.c:66:1: warning: no previous prototype for 'dv_bfin_mmr_require' devices.c:99:1: warning: no previous prototype for 'dv_bfin_mmr_check' devices.c:159:14: warning: no previous prototype for 'dv_get_bus_num' Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2012-03-29Commit gdb and sim support for v850e2 and v850e2v3 on behalf ofKevin Buettner9-26/+3235
Rathish C <Rathish.C@kpitcummins.com>.
2012-03-27sim: add bugzilla markingMike Frysinger1-0/+1
2012-03-26sim: add a proper sim_core_trans_addr prototypeMike Frysinger4-1/+16
The common code has a sim_core_trans_addr() helper that only the m32r code uses. Move the inline extern in the m32r code to the proper common header. Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2012-03-25sim: bfin: skip .c/.S tests if no compiler is availableMike Frysinger2-0/+34
Similar to logic in the cris exp, attempt a simple compile and if it fails (presumably due to the compiler being broken), skip all the related tests. Fortunately, most tests (~600 out of ~800) are pure assembly, so people should still get pretty good coverage. Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2012-03-25sim: bfin: disable redundant test that makes 32bit gas angryMike Frysinger2-1/+7
2012-03-25sim: bfin: fix typos in large constants in testsMike Frysinger6-5/+13
Truncate constants that are larger than 32bits but get loaded into 32bit registers. These high bits don't get used and don't really make sense.
2012-03-24 * nrun.c: Add #ifdef HAVE_CONFIG_H and associated includes stanzaHans-Peter Nilsson2-0/+11
missing in last change.
2012-03-24[PATCH] sim: make sure to include strsignal prototypeMike Frysinger104-3403/+6118
Before POSIX standardized strsignal(), old systems would hide the prototype unless the normal extension defines were enabled. So use the AC_USE_SYSTEM_EXTENSIONS helper for that. Then make sure we include string.h ourselves in nrun.c rather than relying on implicit includes via other sim headers. Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2012-03-24sim: testsuite: regen configure after rl78 additionMike Frysinger1-0/+4
2012-03-24sim: cris: update testsuite output after strsignal changeMike Frysinger25-24/+33
2012-03-23sim: testsuite: regen configure after rl78 additionMike Frysinger1-0/+3
2012-03-23sim: rx: fix warnings with AC_DEFINEMike Frysinger2-3/+8
This lets `autoheader` work again. Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2012-03-23sim: sync build_warnings handling with gdbMike Frysinger2-26/+44
The sim code gets the logic for SIM_AC_OPTION_WARNINGS from gdb, but it hasn't been updated in a good long while. Sync with the latest gdb code. There is a sim specific change in here: we disable -Werror for now. This is because all sim code atm contains warnings. Will probably have to slowly add a white list of targets which can tolerate this until everyone is updated. Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2012-03-21sim: cris: update testsuite output after strsignal changeMike Frysinger38-37/+50
2012-03-21sim/testsuite/: split up arch-specific changelogsMike Frysinger7-613/+587
2012-03-19sim: bfin: add exhaustive parallel-insn testsMike Frysinger4-0/+33517
2012-03-19sim: bfin: unify se_all*opcodes testsMike Frysinger4-287/+255
The current se_all*opcodes tests are very similar in how they work. In preparation for adding more tests along these lines, unify the common bits into a framework that others can include and build off of easily. Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2012-03-19sim: bfin: add tests for new shift behaviorMike Frysinger2-0/+11
2012-03-19sim: bfin: add tests for new shift behaviorMike Frysinger4-0/+137
2012-03-19sim: bfin: fix corner case Logical shift issuesMike Frysinger2-45/+64
From: Robin Getz <robin.getz@analog.com> Overflow with shift operations happens independently of saturation, but we have the logic merged. Extend the lshift function so that callers can tell it when to handle each independently, and then do so when it's needed. Signed-off-by: Robin Getz <robin.getz@analog.com> Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2012-03-19sim: use character classes rather than rangesMike Frysinger4-18/+25
A-Z ranges don't work in all locales, so use character classes instead. Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2012-03-19sim: nrun: decode signal when crashingMike Frysinger2-1/+6
This isn't entirely correct in that it assumes the signal numbering of the target and host match, but seeing as we already make that assumption in a few places, this patch doesn't make the situation any worse. Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2012-03-19sim: tests: ignore generated testsMike Frysinger2-0/+5
2012-03-19sim: bfin: ebiu_amc: push down hardcoded base addressesMike Frysinger2-2/+12
To make it easier to support ebiu banks at other addresses, move the base to a runtime parameter rather than structure. Future work will make this more dynamic, but I'm waiting for more details first. Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2012-03-19sim: bfin: import optimizations from 32bit test into 16bit testMike Frysinger2-35/+73
The 32bit allopcodes test had quite a bit of optimization added to it so that it ran in a reasonable amount of time out of uncached memory. Port those changes over to the 16bit test so the two share common code. Signed-off-by: Mike Frysinger <vapier@gentoo.org>
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