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2008-05-09 * ppc/altivec.igen (vperm): Latch inputs into temporaries.Joel Brobecker2-2/+11
2008-05-05Added 3 miscellaneous testcases like read32.ms uread16.ms hw-trap.ms.M R Swami Reddy3-0/+44
2008-05-05These files removed.M R Swami Reddy3-131/+0
2008-05-05Add the change for testcases comment update and new testcases addition.M R Swami Reddy1-0/+14
2008-05-05Update testcase comment.M R Swami Reddy53-60/+315
addb.cgs addd.cgs addi.cgs andb.cgs andd.cgs andw.cgs ashub.cgs ashub_i.cgs ashud.cgs ashud_i.cgs ashuw.cgs ashuw_i.cgs cmpi.cgs cmpw.cgs jlt.cgs jump.cgs loadd.cgs loadw.cgs lshb.cgs lshb_i.cgs lshd.cgs lshd_i.cgs lshw.cgs lshw_i.cgs movb.cgs movd.cgs movw.cgs movxb.cgs movxw.cgs movzb.cgs movzw.cgs mulb.cgs muluw.cgs mulw.cgs orb.cgs ord.cgs orw.cgs pop1.cgs pop2.cgs pop3.cgs popret1.cgs popret2.cgs popret3.cgs push1.cgs push2.cgs push3.cgs Added BIT operation testcases: cbitb.cgs cbitw.cgs sbitb.cgs sbitw.cgs tbitb.cgs tbit.cgs and tbitw.cgs
2008-05-05Comment changeM R Swami Reddy1-2/+2
2008-05-05Updated the sim engine's ecode logic and commit the code changesM R Swami Reddy1-0/+6
2008-05-05Update for code standardsM R Swami Reddy1-70/+62
2008-05-05Cleaned up unwanted code and fixed BIT operations simulation.M R Swami Reddy1-66/+14
2008-05-05Update simops struct members and PSR bits.M R Swami Reddy1-11/+12
2008-05-05Fix typo.M R Swami Reddy1-3/+3
2008-05-05 Update the machine code decode algorithm using hash table.M R Swami Reddy1-456/+584
2008-04-142008-04-14 Hans Kester <kester.hans@gmail.com>Daniel Jacobowitz2-1/+5
* sim-signal.c: Define missing signals for _WIN32.
2008-04-08 allinsn.exp: Removed target_alias and global_ld_options.M R Swami Reddy2-2/+4
2008-04-08Modified Files:M R Swami Reddy1-0/+7
ChangeLog: Add simulator for National cr16 processor. * cr16: New directory with cr16 simulator files. * configure.ac: Add an entry for National cr16 target. * configure: Regenerate.
2008-04-08Added Files:M R Swami Reddy10-0/+14538
ChangeLog config.in configure configure.ac cr16_sim.h endian.c gencode.c interp.c Makefile.in simops.c: Add these file for CR16 target simulator.
2008-04-08 * configure.ac: Add an entry for National CR16 target.M R Swami Reddy2-0/+12
* configure: Regenerate.
2008-04-08 ChangeLog: sim/cr16/: New directory. Added tests for CR16 simulator.M R Swami Reddy1-0/+43
2008-04-08 ChangeLog: New fileM R Swami Reddy1-0/+23
2008-04-08 New files: Testcases for cr16 instruction set.M R Swami Reddy123-0/+2714
2008-04-08 testutils.inc: New file: Test macros for cr16 target.M R Swami Reddy1-0/+72
2008-04-08 allinsn.exp misc.exp: New files: Test run scriptsM R Swami Reddy2-0/+45
2008-04-08 gennltvals.sh: Add cr16 target sys macros.M R Swami Reddy3-0/+45
nltvals.def: Rebuild.
2008-04-08Updated the MAINTAINERS file: Add myself as maintainer of cr16 port.M R Swami Reddy1-0/+4
2008-04-08Add myself as maintainer of cr16 port.M R Swami Reddy1-0/+1
2008-03-14 * configure.ac: Pass ../../intl to ZW_GNU_GETTEXT_SISTER_DIR.Nick Hudson3-3/+8
* configure: Regenerate.
2008-02-06* simops.c (OP_1C007E0): Compensate for 64 bit hosts.DJ Delorie3-9/+17
(OP_18007E0): Likewise. (OP_2C007E0): Likewise. (OP_28007E0): Likewise. * v850.igen (divh): Likewise.
2008-02-06Index: ChangeLogDJ Delorie23-100/+1579
* configure.ac (v850): V850 now has a testsuite. * configure (v850): Likewise. Index: testsuite/ChangeLog * sim/v850/: New directory. * sim/v850/allinsns.exp: New. * sim/v850/bsh.cgs: New. * sim/v850/div.cgs: New. * sim/v850/divh.cgs: New. * sim/v850/divh_3.cgs: New. * sim/v850/divhu.cgs: New. * sim/v850/divu.cgs: New. * sim/v850/sar.cgs: New. * sim/v850/satadd.cgs: New. * sim/v850/satsub.cgs: New. * sim/v850/satsubi.cgs: New. * sim/v850/satsubr.cgs: New. * sim/v850/shl.cgs: New. * sim/v850/shr.cgs: New. * sim/v850/testutils.cgs: New. * sim/v850/testutils.inc: New. Index: v850/ChangeLog * simops.c (OP_C0): Correct saturation logic. (OP_220): Likewise. (OP_A0): Likewise. (OP_660): Likewise. (OP_80): Likewise. * simops.c (OP_2A0): If the shift count is zero, clear the carry. (OP_A007E0): Likewise. (OP_2C0): Likewise. (OP_C007E0): Likewise. (OP_280): Likewise. (OP_8007E0): Likewise. * simops.c (OP_2C207E0): Correct PSW flags for special divu conditions. (OP_2C007E0): Likewise, for div. (OP_28207E0): Likewise, for divhu. (OP_28007E0): Likewise, for divh. Also, sign-extend the correct operand. * v850.igen (divh): Likewise, for 2-op divh. * v850.igen (bsh): Fix carry logic.
2008-02-042008-02-04 Antony King <antony.king@st.com>Andrew Stubbs2-13/+12
* interp.c (macl): Fix non-portable implementation.
2008-01-01 Updated copyright notices for most files.Daniel Jacobowitz295-294/+323
2007-12-19* frv/frv.c (frvbf_cut): Only look at the six LSBs ofDJ Delorie2-0/+6
cut_point.
2007-11-08 * sim/cris/asm/x0-v10.ms, sim/cris/asm/x0-v32.ms: TweakHans-Peter Nilsson3-4/+9
stack-pointer match pattern for 4K host environment.
2007-10-22sim/mips/Richard Sandiford2-23/+98
* mips.igen (check_fmt_p): Provide a separate mips32r2 definition that unconditionally allows fmt_ps. (ALNV.PS, CEIL.L.fmt, CVT.L.fmt, CVT.PS.S, CVT.S.PL, CVT.S.PU) (FLOOR.L.fmt, LWXC1, MADD.fmt, MSUB.fmt, NMADD.fmt, NMSUB.fmt) (PLL.PS, PLU.PS, PUL.PS, PUU.PS, ROUND.L.fmt, TRUNC.L.fmt): Change filter from 64,f to 32,f. (PREFX): Change filter from 64 to 32. (LDXC1, LUXC1): Provide separate mips32r2 implementations that use do_load_double instead of do_load. Make both LUXC1 versions unpredictable if SizeFGR () != 64. (SDXC1, SUXC1): Extend to mips32r2, using do_store_double instead of do_store. Remove unused variable. Make both SUXC1 versions unpredictable if SizeFGR () != 64.
2007-10-22 * sim/cris/asm/testutils.inc (test_move_cc): Add missing call toHans-Peter Nilsson14-31/+225
test_cc. * sim/cris/asm/asr.ms: Correct expected condition code flags. * sim/cris/asm/boundr.ms: Ditto. * sim/cris/asm/dstep.ms: Ditto. * sim/cris/asm/lsr.ms: Ditto. * sim/cris/asm/movecr.ms: Ditto. * sim/cris/asm/mover.ms: Ditto. * sim/cris/asm/neg.ms: Ditto. Use test_cc, not test_move_cc. * sim/cris/asm/op3.ms: Check the condition code flags after the insn under test. * sim/cris/asm/movecrt10.ms: Update expected number of simulated cycles. * sim/cris/asm/movecrt32.ms: Ditto. * sim/cris/asm/jsr.ms: Don't use local label 8. * sim/cris/asm/nonvcv32.ms: New test.
2007-10-22 * cris/arch.c, cris/arch.h, cris/cpuall.h, cris/cpuv10.c,Hans-Peter Nilsson19-222/+265
cris/cpuv10.h, cris/cpuv32.c, cris/cpuv32.h, cris/cris-desc.c, cris/cris-desc.h, cris/cris-opc.h, cris/decodev10.c, cris/decodev10.h, cris/decodev32.c, cris/decodev32.h, cris/modelv10.c, cris/modelv32.c, cris/semcrisv10f-switch.c, cris/semcrisv32f-switch.c: Regenerate.
2007-10-15 * NEWS: Document target described register support for PowerPC.Daniel Jacobowitz2-5/+14
* ppc-tdep.h: Remove ppc_spr constants. (struct gdbarch_tdep): Remove regs, ppc_sr0_regnum, and ppc_builtin_type_vec128 members. (PPC_R0_REGNUM, PPC_F0_REGNUM, PPC_PC_REGNUM, PPC_MSR_REGNUM) (PPC_CR_REGNUM, PPC_LR_REGNUM, PPC_CTR_REGNUM, PPC_XER_REGNUM) (PPC_FPSCR_REGNUM, PPC_MQ_REGNUM, PPC_SPE_UPPER_GP0_REGNUM) (PPC_SPE_ACC_REGNUM, PPC_SPE_FSCR_REGNUM, PPC_VR0_REGNUM) (PPC_VSCR_REGNUM, PPC_VRSAVE_REGNUM, PPC_NUM_REGS): New constants. * rs6000-tdep.c: Include preparsed descriptions. (init_sim_regno_table): Do not iterate over pseudo registers. Look up segment registers by name. Use sim_spr_register_name for SPRs. (rs6000_register_sim_regno): Call init_sim_regno_table here. (rs6000_builtin_type_vec128): Delete. (rs6000_register_name): Only handle SPE pseudo registers and upper halves. Call tdesc_register_name for everything else. (rs6000_register_type): Delete. Replace with... (rs6000_pseudo_register_type): ...this new function. Only handle SPE pseudo registers. (rs6000_register_reggroup_p): Delete. Replace with... (rs6000_pseudo_register_reggroup_p): ...this new function. Only handle SPE pseudo registers. (rs6000_convert_register_p): Use ppc_fp0_regnum instead of "struct reg". (rs6000_register_to_value, rs6000_value_to_register): Remove check of reg->fpr. (e500_register_reggroup_p): Delete. (STR, R, R4, R8, R16, F, P8, R32, R64, R0, A4, S, S4, SN4, S64) (COMMON_UISA_REGS, PPC_UISA_SPRS, PPC_UISA_NOFP_SPRS) (PPC_SEGMENT_REGS, PPC_OEA_SPRS, PPC_ALTIVEC_REGS, PPC_SPE_GP_REGS) (PPC_SPE_UPPER_GP_REGS, PPC_EV_PSEUDO_REGS): Delete macros. (registers_powerpc, registers_403, registers_403GC, registers_505) (registers_860, registers_601, registers_602, registers_603) (registers_604, registers_750, registers_7400, registers_e500): Delete variables. (struct variant): Delete nregs, npregs, num_tot_regs, and regs. Add tdesc. (tot_num_registers, num_registers, num_pseudo_registers): Delete. (variants): Delete outdated comment. Use standard target descriptions instead of "struct reg" arrays. (init_variants): Delete. (rs6000_gdbarch_init): Do not guess word size from the BFD architecture if we have a target description. Select a variant before creating a new architecture. Use the variant's target description if the target did not define a register layout. Validate target-supplied registers. Reject mismatches. Use fixed register numbers and new constants instead of magic numbers. Call set_gdbarch_ps_regnum. Call tdesc_use_registers. (_initialize_rs6000_tdep): Initialize the preparsed target descriptions. * target-descriptions.c (tdesc_predefined_types): Add int128 and uint128. (tdesc_find_register_early): New function. (tdesc_numbered_register): Use it. (tdesc_register_size): New function. (tdesc_use_registers): Take a target_desc argument. Do not use gdbarch_target_desc. * target-descriptions.h (tdesc_use_registers): Update prototype and comment. (tdesc_register_size): New prototype. * Makefile.in (powerpc_32_c, powerpc_403_c, powerpc_403gc_c) (powerpc_505_c, powerpc_601_c, powerpc_602_c, powerpc_603_c) (powerpc_604_c, powerpc_64_c, powerpc_7400_c, powerpc_750_c) (powerpc_860_c, powerpc_e500_c, rs6000_c): New macros. (rs6000-tdep.o): Update. * arm-tdep.c (arm_gdbarch_init): Update call to tdesc_use_registers. * m68k-tdep.c (m68k_gdbarch_init): Likewise. * mips-tdep.c (mips_gdbarch_init): Likewise. * gdb.texinfo (Predefined Target Types): Add int128 and uint128. (Standard Target Features): Add PowerPC features. * gdb.xml/tdesc-regs.exp: Add PowerPC support. * sim-ppc.h (sim_spr_register_name): New prototype. * gdb-sim.c (regnum2spr): Rename to... (sim_spr_register_name): ... this. Make global.
2007-10-112007-10-11 Jesper Nilsson <jesper.nilsson@axis.com>Daniel Jacobowitz6-8/+60
* callback.c (cb_is_stdin, cb_is_stdout, cb_is_stderr): Add functions. * syscall.c (cb_syscall): Test for stdin/out/err, not just fd 0/1/2. 2007-10-11 Jesper Nilsson <jesper.nilsson@axis.com> * callback.h (cb_is_stdin, cb_is_stdout, cb_is_stderr): Add prototypes. 2007-10-11 Jesper Nilsson <jesper.nilsson@axis.com> * sim/cris/c/freopen2.c: Added testcase.
2007-10-112007-10-11 Jesper Nilsson <jesper.nilsson@axis.com>Daniel Jacobowitz3-1/+13
* callback.c (cb_is_stdin): Add. * syscall.c (cb_syscall): Test for stdin, not just fd 0. 2007-10-11 Jesper Nilsson <jesper.nilsson@axis.com> * callback.h (cb_is_stdin): Add prototype.
2007-10-082007-09-24 Andrew Stubbs <andrew.stubbs@st.com>Denis Pilat2-0/+8
* gencode.c (tab): Add RAISE_EXCEPTION_IF_IN_DELAY_SLOT to the definition of PC relative 'mov.l'/'mov.w' and also 'mova'.
2007-10-07sim/mips/Richard Sandiford2-7/+17
* mips.igen (ll): Fix mask for WITH_TARGET_WORD_BITSIZE == 32. (sc, swxc1): Likewise. Also fix big-endian and reverse-endian shifts for that case.
2007-09-04* interp.c (options enum): Add OPTION_INFO_MEMORY.Nick Clifton2-0/+56
(display_mem_info): New static variable. (mips_option_handler): Handle OPTION_INFO_MEMORY. (mips_options): Add info-memory and memory-info. (sim_open): After processing the command line and board specification, check display_mem_info. If it is set then call the real handler for the --memory-info command line switch.
2007-09-04 * sim/ppc/emul_bugapi.c (emul_bugapi_create): quote the fileJerome Guitton2-2/+12
name property before parsing it.
2007-08-28 * compare_igen_models: Change license to GPL version 3.Joel Brobecker2-7/+10
2007-08-28 * configure.ac: Change license of multi-run.c to GPL version 3.Joel Brobecker3-8/+11
* configure: Regenerate.
2007-08-28 * lf.c (lf_print__gnu_copyleft): Change license to GPL version 3.Joel Brobecker2-6/+8
2007-08-28 * testutils.inc: Change license to GPL version 3.Joel Brobecker5-20/+23
* utils-dsp.inc: Change license to GPL version 3. * utils-fpu.inc: Change license to GPL version 3. * utils-mdmx.inc: Change license to GPL version 3.
2007-08-24 Switch the license of all files explicitly copyright the FSFJoel Brobecker381-2073/+1572
to GPLv3.
2007-08-10* sim-memopt.c (memory_options): Mention that the memory-size switch accepts ↵Nick Clifton3-7/+47
suffixes. (parse_size): Handle a suffix on the size value. * sim-options.c (standard_options): Mention that the mem-size switch accepts suffixes. (standard_option_handler): Handle a suffix on the size value.
2007-07-032007-07-03 Yoshinori Sato <ysato@users.sourceforge.jp>Daniel Jacobowitz2-1/+6
* compile.c (sim_resume): Fix the last byte of ARGV for SYS_CMDLINE.
2007-06-28sim/mips/Richard Sandiford3-36/+44
* configure.ac, configure: Revert last patch.
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