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AgeCommit message (Expand)AuthorFilesLines
2015-11-16sim: sim-stop/sim-reason/sim-reg: move to common obj listMike Frysinger44-56/+119
2015-11-15sim: cr16: drop global callback stateMike Frysinger4-62/+70
2015-11-15sim: cr16: convert to common sim engine logicMike Frysinger5-157/+96
2015-11-15sim: cr16: convert to common sim memory modulesMike Frysinger8-589/+62
2015-11-15sim: cr16: push down sd/cpu varsMike Frysinger6-788/+833
2015-11-15sim: cr16: delete unused memory helpersMike Frysinger3-20/+6
2015-11-15sim: cr16: switch to common sim-regMike Frysinger3-13/+61
2015-11-15sim: cr16/d10v: drop redundant call to sim_create_inferiorMike Frysinger4-2/+8
2015-11-15sim: d10v: drop global callback stateMike Frysinger4-137/+149
2015-11-15sim: d10v: convert to common sim engine logicMike Frysinger5-218/+137
2015-11-15sim: d10v: push down sd/cpu varsMike Frysinger6-500/+543
2015-11-15sim: h8300: convert to common sim_{reason,stop}Mike Frysinger3-15/+8
2015-11-15sim: mcore: pull cpu state out of global scopeMike Frysinger3-294/+309
2015-11-15sim: mcore: switch to common sim-regMike Frysinger3-4/+16
2015-11-15sim: mcore: add a fail testcaseMike Frysinger3-1/+14
2015-11-15sim: mcore: convert to common reason/resume logicMike Frysinger3-40/+64
2015-11-15sim: clean up redundant objectsMike Frysinger8-20/+19
2015-11-15sim: sim-close: unify sim_close logicMike Frysinger50-171/+173
2015-11-15sim: m32c: add a basic testsuiteMike Frysinger5-0/+92
2015-11-15sim: testsuite: support basic vars in flagsMike Frysinger2-1/+12
2015-11-10Update the RX simulator to handle the latest opcode types.Nick Clifton2-1/+24
2015-11-10sim: cr16/d10v: localize translation funcsMike Frysinger4-6/+18
2015-11-10sim: m32c: move test code to testsuiteMike Frysinger8-26/+17
2015-11-10sim: m32c: drop redundant dependency infoMike Frysinger2-13/+4
2015-11-10sim: h8300: drop unused littleendian variableMike Frysinger2-13/+5
2015-10-12sim: ft32: test coverage for link parameters and PM write portJames Bowman2-0/+42
2015-10-11sim: moxie: fix leakage in error path [BZ #18273]Mike Frysinger2-0/+6
2015-10-11sim: bfin: handle negative left saturated shifts as ashifts [BZ #18407]Mike Frysinger4-1/+33
2015-09-29sim: ft32: correct simulation of MEMCPY and MEMSETJames Bowman2-2/+7
2015-09-29sim: ft32: correctly simulate PM write portJames Bowman2-2/+10
2015-09-25[PATCH] Add micromips support to the MIPS simulatorAndrew Bennett22-1468/+7290
2015-09-22sim: ft32: add character input portJames Bowman2-0/+6
2015-08-05Fix building GDB for the M32C by providing a stub sim_info function.Nick Clifton2-0/+11
2015-07-24Remove leading/trailing white spaces in ChangeLogH.J. Lu31-1219/+1219
2015-07-14Remove extraneous whitespace from ARM sim sources.Nick Clifton29-320/+348
2015-07-02Fix snafu with latest addition to the ARM sim.Nick Clifton2-1/+7
2015-06-28Add support for ARM v6 instructions.Nick Clifton9-126/+3881
2015-06-24sim: trace: drop unused trace_one_insnMike Frysinger3-98/+5
2015-06-24sim: trace: rename debug_printf fullyMike Frysinger3-5/+10
2015-06-24sim: trace: add a basic cpu register classMike Frysinger8-42/+56
2015-06-24sim: trace: add set of system helpersMike Frysinger2-0/+28
2015-06-24sim: trace: document alu/fpu/vpu trace options betterMike Frysinger3-7/+14
2015-06-23sim: common: replace SIM_FILTER_PATH with lbasenameMike Frysinger3-26/+16
2015-06-23sim: use AS_HELP_STRING everywhereMike Frysinger60-368/+791
2015-06-23sim: trace: do not enable internal debug by defaultMike Frysinger2-2/+6
2015-06-23sim: assume recentish compiler/systemsMike Frysinger6-43/+14
2015-06-21sim: common: add basic model assertMike Frysinger2-0/+5
2015-06-21sim: common: use standard intXX_t types for signedXXMike Frysinger2-82/+27
2015-06-21sim: common: standardize multiple include definesMike Frysinger6-13/+26
2015-06-18sim: syscall: simplify unknown syscall traceMike Frysinger2-5/+7
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