aboutsummaryrefslogtreecommitdiff
path: root/sim
AgeCommit message (Expand)AuthorFilesLines
2015-06-21sim: common: add basic model assertMike Frysinger2-0/+5
2015-06-21sim: common: use standard intXX_t types for signedXXMike Frysinger2-82/+27
2015-06-21sim: common: standardize multiple include definesMike Frysinger6-13/+26
2015-06-18sim: syscall: simplify unknown syscall traceMike Frysinger2-5/+7
2015-06-18sim: callback: fix sentinel testing when walking mapsMike Frysinger2-2/+7
2015-06-17sim: syscall: add common sim_syscall helpersMike Frysinger15-171/+197
2015-06-17sim: syscall: unify memory helpersMike Frysinger20-214/+167
2015-06-17sim: callback: add human readable strings for debugging to mapsMike Frysinger7-675/+768
2015-06-12sim: bfin: expand CB_SYS_xxx commentMike Frysinger2-1/+7
2015-06-12sim: update configure.in->configure.ac docsMike Frysinger62-40/+162
2015-06-12sim: drop -DTRACE from configureMike Frysinger55-84/+193
2015-06-12sim: msp430: use new common trace print helpersMike Frysinger2-109/+69
2015-06-12sim: moxie: use new common trace definesMike Frysinger2-4/+14
2015-06-12sim: trace: add common macros for logging infoMike Frysinger8-37/+74
2015-06-12sim: mips: switch to common WITH_TRACE_ANY_PMike Frysinger4-30/+36
2015-06-12sim: trace: add WITH_TRACE_ANY_P helperMike Frysinger4-8/+19
2015-06-12sim: moxie: rename TRACE to MOXIE_TRACE_INSNMike Frysinger2-73/+79
2015-06-12sim: cgen: namespace custom trace functionsMike Frysinger43-7039/+7143
2015-06-11sim: msp430: delete unused trace macrosMike Frysinger2-48/+6
2015-06-11sim: trace: centralize the system tracingMike Frysinger4-17/+14
2015-06-11sim: trace: add STRACE_xxx_P macrosMike Frysinger2-0/+21
2015-06-11sim: trace: use existing defines for the useful maskMike Frysinger2-4/+5
2015-06-11sim: trace: create a common WITH_TRACE_P macroMike Frysinger2-19/+28
2015-06-11sim: frv: drop custom debug maskMike Frysinger2-5/+4
2015-06-11sim: m68hc11: delete unused interrupt_namesMike Frysinger2-8/+4
2015-06-11sim: m68hc11: switch to common sim_resumeMike Frysinger3-77/+7
2015-06-11sim: mn10300: delete unused memory codeMike Frysinger4-62/+19
2015-06-11sim: mn10300: add missing static markingsMike Frysinger2-2/+6
2015-06-11sim: mn10300: delete unused exception/exited/debug stateMike Frysinger4-22/+11
2015-06-11sim: mn10300: use common size typesMike Frysinger2-29/+12
2015-06-11sim: m68hc11/mn10300/v850: delete redundant INLINE definesMike Frysinger7-32/+13
2015-06-11sim: microblaze: switch to common sim_resume/sim_stop_reasonMike Frysinger4-28/+27
2015-06-09Fix latest sim/common/ChangeLog entry.Joel Brobecker1-1/+0
2015-06-09Remove unnecessary empty line in sim/common/ChangeLogJoel Brobecker1-1/+0
2015-06-09Fix spelling mistakes in sim/common/sim-events.c error messages.Mike Stump2-1/+7
2015-05-17sim: erc32: restore attributionMike Frysinger8-7/+33
2015-05-08Switch erc32 simulator copyright headers to FSF.Joel Brobecker11-150/+158
2015-04-30Make RL78 disassembler and simulator respect ISA for mul/divDJ Delorie9-11/+121
2015-04-29Fix problems in the sim sources discovered by running the cppcheck static ana...Nick Clifton8-6/+29
2015-04-27sim: avr: Fix 'multiple definition of sim_{read,write}'Senthil Kumar Selvaraj2-1/+6
2015-04-24Fix typos in sim sources exposed by static analysis.Nick Clifton6-4/+23
2015-04-24Fix typo in check for valid register number in RX sim.Nick Clifton2-1/+6
2015-04-21sim: mcore: clean up printf warningsMike Frysinger2-8/+13
2015-04-21sim: mcore: convert to common memory/verbose functionsMike Frysinger2-319/+59
2015-04-21sim: mcore: drop watchpoint/dumpmem/clearstats supportMike Frysinger2-73/+12
2015-04-21sim: mcore: switch to common syscall handlingMike Frysinger6-140/+64
2015-04-21sim: gennltvals.sh: handle split out newlib source treeMike Frysinger5-17/+32
2015-04-19sim/erc32: Switched emulated memory to host endian order.Jiri Gaisler7-210/+159
2015-04-18sim: clean up duplicate sim-engine hooksMike Frysinger8-37/+17
2015-04-18sim: trim old USING_SIM_BASE_H defineMike Frysinger12-12/+24
generated by cgit v1.1 at 2024-12-04 10:01:00 +0000