| Age | Commit message (Collapse) | Author | Files | Lines |
|---|
|
* Makefile.in (SIM_EXTRA_CFLAGS): Revert previous delta.
(SIM_EXTRA_LIBS): Add -lm.
|
|
* Makefile.in (SIM_EXTRA_CFLAGS): Add -lm.
* armdefs.h (ARMdval, ARMfval): New types.
(ARM_VFP_reg): New union.
(struct ARMul_State): Add VFP_Reg and FPSCR fields.
(VFP_fval, VFP_uword, VFP_sword, VFP_dval, VFP_dword): Accessor
macros for the new VFP_Reg field.
* armemu.c (handle_v6_insn): Add code to handle MOVW, MOVT,
QADD16, QASX, QSAX, QSUB16, QADD8, QSUB8, UADD16, USUB16, UADD8,
USUB8, SEL, REV, REV16, RBIT, BFC, BFI, SBFX and UBFX
instructions.
(handle_VFP_move): New function.
(ARMul_Emulate16): Add checks for newly supported v6
instructions. Add support for VMRS, VMOV and MRC instructions.
(Multiply64): Allow nRdHi == nRm and/or nRdLo == nRm when
operating in v6 mode.
* armemu.h (t_resolved): Define.
* armsupp.c: Include math.h.
(handle_VFP_xfer): New function. Handles VMOV, VSTM, VSTR, VPUSH,
VSTM, VLDM and VPOP instructions.
(ARMul_LDC): Test for co-processor 10 or 11 and pass call to the
new handle_VFP_xfer function.
(ARMul_STC): Likewise.
(handle_VFP_op): New function. Handles VMLA, VMLS, VNMLA, VNMLS,
VNMUL, VMUL, VADD, VSUB, VDIV, VMOV, VABS, VNEG, VSQRT, VCMP,
VCMPE and VCVT instructions.
(ARMul_CDP): Test for co-processor 10 or 11 and pass call to the
new handle_VFP_op function.
* thumbemu.c (tBIT, tBITS, ntBIT, ntBITS): New macros.
(test_cond): New function. Tests a condition and returns non-zero
if the condition has been met.
(handle_IT_block): New function.
(in_IT_block): New function.
(IT_block_allow): New function.
(ThumbExpandImm): New function.
(handle_T2_insn): New function. Handles T2 thumb instructions.
(handle_v6_thumb_insn): Add next_instr and pc parameters.
(ARMul_ThumbDecode): Add support for IT blocks. Add support for
v6 instructions.
* wrapper.c (sim_create_inferior): Detect a thumb address and call
SETT appropriately.
|
|
Everyone has migrated to the split functions (trace_prefix + trace_generic)
a while ago, so we can drop this one now.
|
|
Rather than redirect using a define, just rename the symbol fully.
|
|
The bfin/msp430 ports already had trace logic set up for reading/writing
cpu registers, albeit using different unrelated levels (core & vpu). Add
a proper register class for these and for other ports.
|
|
Some code paths trace on a system instance and not a cpu instance (like
the events code), so add some helpers for those cases.
|
|
Make the acronyms clear for people.
|
|
This helper macro has largely the same behavior as libiberty's lbasename.
There is a slight nuance related to colons, but it's not clear what the
point of that is, and the code implies that it just wants the basename.
|
|
This helps standardize the configure --help output.
|
|
Since --trace-debug is for people hacking on the sim sources rather than
people just using the sim, default it to off. This matches the behavior
of other debug knobs we have.
|
|
Assume the build system supports stdint.h/stdarg.h as those have been
around long enough and we don't care about pre-stdc compilers anymore.
|
|
If the configured in default doesn't match a known value, throw an
assertion failure rather than segfaulting deeper down.
|
|
Let's assume that the system supports the POSIX int8/16/32/64_t types
as this collapses the logic significantly.
|
|
We use SIM_xxx_H in most headers, so convert _SIM_xxx_H_ over to it.
|
|
Since we always include the raw syscall number when tracing, also
including it in the name when it's unknown is redundant. Simplify
the code by using a constant string.
|
|
The new helpers for walking the maps tested the wrong value for exiting
the for loop. This caused crashes when looking up entries that were not
in the map.
|
|
Many ports have the same sim syscall logic, so add some helpers to handle
all the common details. The arches still have to deal with the unpacking
and packing of the syscall arguments, but the rest of the sim<->callback
glue is now shared.
|
|
Almost every port implements these two callbacks in the same way, so
unify them in the common layer.
|
|
When tracing, we often want to display the human readable name for the
various syscall/errno values. Rather than make each target duplicate
the lookup, extend the existing maps to include the string directly,
and add helper functions to look up the constants.
While most targets are autogenerated (from libgloss), the bfin/cris
targets have custom maps for the Linux ABI which need to be updated
by hand.
|
|
|
|
A few places still refer to the configure.in file; update them.
|
|
No code uses this anymore and the symbol conflicts with the new TRACE
helper. Punt it from configure.
|
|
Replace the "if (TRACE_xxx_P) trace_generic" form with "TRACE_xxx".
The output is the same, but the code is nicer to read.
|
|
Now that there's common helpers for printing trace data, switch to that
to restore the insn tracing support for this target.
|
|
The Blackfin port had some TRACE_xxx macros for easily logging trace data.
Use these as a base for common ones that have a simple form and match the
existing sets of helper macros.
|
|
We want to add new common trace helpers including "TRACE", so change the
mips one to the new WITH_TRACE_ANY_P macro since they do the same thing.
|
|
We have STRACE_ANY_P and TRACE_ANY_P, so add WITH_TRACE_ANY_P to fill
out the API. This lets us wrap the internal configure symbol.
|
|
We want to add new common trace helpers including "TRACE", so rename the
moxie one to MOXIE_TRACE_INSN. This also matches what the code is doing.
|
|
The cgen code declares some macros/funcs using the trace_xxx prefix, but
the code isn't generic and only works with cgen targets. This is blocking
the creation of new common trace functions.
Let's blindly add cgen_xxx prefixes to all these symbols. Some already
use this convention to avoid conflicts, so it makes sense to align them.
In the future we might want to move some to the common trace core, but
one thing at a time.
|
|
These macros were copied from the Blackfin port but never used, so delete
them as part of the trace unification work.
|
|
First we convert the ETRACE_P to STRACE_EVENTS_P. This means we move from
using the sim_events.trace storage to the common sim_state_base.trace_data
array. With that deleted, the common trace init code can be simplified so
the sim state works the same as the sim cpu.
|
|
These are the parallel to the TRACE_xxx_P macros and fill out the full
set to match the existing debug one.
|
|
No point in duplicating the shift logic when we have macros already to
keep that all unified.
|
|
This way we can use the IDX macros everywhere and not worry about the
encoding of the WITH_TRACE define in multiple places.
|
|
This is the only sim that sets up its own WITH_TRACE mask and it conflicts
with the user setting their own list at configure time. Drop it to match
all the other sims.
|
|
The interrupts.c file has a static/fuller definition that is used,
so drop this copy in interp.c.
|
|
This code already matched the common sim reusme logic, so we can simply
drop it and pull in the common code.
|
|
Only one place used get_word/put_word, so inline the usage there.
All the rest is dead code so trim it.
|
|
|
|
The syscall path was the only code checking the custom exception state
after recent cleanups. Once we change that to the common engine halt
function, we can delete that state entirely.
This also helps highlight some other dead code that we can cull.
|
|
No point in open coding this logic here when we have common size types
already that give the right answer.
|
|
The sim-inline.h header already takes care of this for us, so punt
the local definitions.
|
|
This allows us to use the common code for all exception handling.
|
|
|
|
|
|
sim/common/ChangeLog:
* sim-events.c (sim_events_schedule_after_signal): Fix spelling
mistake in call to sim_engine_abort.
(sim_events_schedule_after_signal): Likewise.
|
|
|
|
Permission was granted by Jiri Gaisler, who has a copyright assignment
on file for GDB.
sim/erc32/ChangeLog:
* configure.ac: Add copyright header.
* erc32.c: Change copyright holder to FSF. Reformat.
* exec.c, float.c, func.c, interf.c, sis.c, sis.h: Likewise.
* help.c, startsim: Add copyright header.
|
|
[gas]
* config/rl78-defs.h (rl78_isa_g10): New.
(rl78_isa_g13): New.
(rl78_isa_g14): New.
* config/rl78-parse.y (ISA_G10): New.
(ISA_G13): New.
(ISA_G14): New.
(MULHU, MULH, MULU, DIVHU, DIVWU, MACHU, MACH): Use them.
* config/tc-rl78.c (rl78_isa_g10): New.
(rl78_isa_g13): New.
(rl78_isa_g14): New.
[gdb]
* rl78-tdep.c (rl78_analyze_prologue): Pass RL78_ISA_DEFAULT to
rl78_decode_opcode
[include]
* dis-asm.h (print_insn_rl78_g10): New.
(print_insn_rl78_g13): New.
(print_insn_rl78_g14): New.
(rl78_get_disassembler): New.
* opcode/rl78.h (RL78_Dis_Isa): New.
(rl78_decode_opcode): Add ISA parameter.
[opcodes]
* disassemble.c (disassembler): Choose suitable disassembler based
on E_ABI.
* rl78-decode.opc (rl78_decode_opcode): Take ISA parameter. Use
it to decode mul/div insns.
* rl78-decode.c: Regenerate.
* rl78-dis.c (print_insn_rl78): Rename to...
(print_insn_rl78_common): ...this, take ISA parameter.
(print_insn_rl78): New.
(print_insn_rl78_g10): New.
(print_insn_rl78_g13): New.
(print_insn_rl78_g14): New.
(rl78_get_disassembler): New.
[sim]
* rl78/cpu.c (g14_multiply): New.
* rl78/cpu.h (g14_multiply): New.
* rl78/load.c (rl78_load): Decode ISA completely.
* rl78/main.c (main): Expand -M to include other ISAs.
* rl78/rl78.c (decode_opcode): Decode based on ISA.
* rl78/trace.c (rl78_disasm_fn): New.
(sim_disasm_init): Reset it.
(sim_disasm_one): Get correct disassembler for ISA.
|
|
analysis tool.
erc32 PR 18273
* sis.c (main): Remove unreachable code.
m68hc11 * gencode.c (gen_fetch_operands): Remove unreachable code.
ppc * hw_htab.c (htab_map_binary): Fix overlap check.
common * sim-fpu.c (INLINE_SIM_FPU): Fix static analysis warning by
increasing parenthesis around casts to signed values.
|
