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2015-04-29Fix problems in the sim sources discovered by running the cppcheck static ↵Nick Clifton8-6/+29
analysis tool. erc32 PR 18273 * sis.c (main): Remove unreachable code. m68hc11 * gencode.c (gen_fetch_operands): Remove unreachable code. ppc * hw_htab.c (htab_map_binary): Fix overlap check. common * sim-fpu.c (INLINE_SIM_FPU): Fix static analysis warning by increasing parenthesis around casts to signed values.
2015-04-27sim: avr: Fix 'multiple definition of sim_{read,write}'Senthil Kumar Selvaraj2-1/+6
This patch does whatever was done in https://sourceware.org/ml/gdb-patches/2015-04/msg00437.html to fix broken gdb build for the AVR target.
2015-04-24Fix typos in sim sources exposed by static analysis.Nick Clifton6-4/+23
bfin PR 18273 * bfin-sim.c (decode_dsp32alu_0): Remove spurious check for s == 1. erc32 PR 18273 * exec.c (add32): Fix typo in check for overflow. igen PR 18273 * misc.c (a2i): Fix typos checking for uppercase letters.
2015-04-24Fix typo in check for valid register number in RX sim.Nick Clifton2-1/+6
PR sim/18273 * reg.c (put_reg): Fix check for valid register number.
2015-04-21sim: mcore: clean up printf warningsMike Frysinger2-8/+13
These printf statements are showing "word" objects which are typedefed from long, so make sure to use l with %x when printing them to avoid warnings from gcc.
2015-04-21sim: mcore: convert to common memory/verbose functionsMike Frysinger2-319/+59
Re-use the existing memory core that handles reads/writes. The verbose command is converted to the common --verbose flag since only a few call sites use it now.
2015-04-21sim: mcore: drop watchpoint/dumpmem/clearstats supportMike Frysinger2-73/+12
In preparation for converting to the common memory framework, the custom commands get in our way. But when we realize that gdb support has been dropped for mcore, it makes things a bit easier: the main runner does not let you run arbitrary commands once simulation starts. So lets disable watchpoint support until it can be converted to the common watchpoint logic. There's already an ifdef to let us do that. We straight up drop support for the dumpmem command (no other sim supports this, and if it's a feature people want, we can add a common func) and the clearstats command (not a big deal -- just restart your simulation). We leave in place the verbose check points as a follow up commit will cut that over to common logic.
2015-04-21sim: mcore: switch to common syscall handlingMike Frysinger6-140/+64
Now that libgloss has a header tracking the syscalls for this arch, we can update the database to include it for the symbolic constants/maps. Then we can switch the mcore syscall callbacks over to the common ones.
2015-04-21sim: gennltvals.sh: handle split out newlib source treeMike Frysinger5-17/+32
Since newlib no longer shares the same repo as binutils/gdb, we have to go searching further afield to locate the sources. We still look at the top level for newlib, but if that is not found, we also try up one dir outside of this source tree. It sucks, but better than the status quo (no workie).
2015-04-19sim/erc32: Switched emulated memory to host endian order.Jiri Gaisler7-210/+159
Change data ordering in emulated memory from target order (big endian) to host order. Improves performance and simplifies most memory operations. Requires some byte twisting during stores on little endian hosts (intel). Also removed support for little-endian binaries.
2015-04-18sim: clean up duplicate sim-engine hooksMike Frysinger8-37/+17
Now that we've unified sim-cpu, we can delete the duplicate sim-engine hooks -- these targets defined these only because they didn't fully implement the sim-cpu callbacks.
2015-04-18sim: trim old USING_SIM_BASE_H defineMike Frysinger12-12/+24
This doesn't appear to have been used since 1998, but wasn't cleaned up since. So much for being "quick" ;).
2015-04-18sim: unify SIM_CPU definitionMike Frysinger46-57/+96
Since every target typedefs this the same way, move it to the common code. We have to leave Blackfin behind here for now because of inter-dependencies on types and headers: sim-base.h includes sim-model.h which needs types in machs.h which needs types in bfim-sim.h which needs SIM_CPU.
2015-04-18sim: unify sim_cia definitionMike Frysinger47-54/+101
Almost every target defines sim_cia the same way -- either using the address_word type directly, or a type of equivalent size. The only odd one out is sh64 (who has 32bit address_word and 64bit cia), and even that case doesn't seem to make sense. We'll put off clean up though of sh64 and at least set up a sensible default for everyone.
2015-04-17sim: microblaze: switch to common memory functionsMike Frysinger4-332/+33
Re-use the existing memory core that handles reads/writes. This drops support for the dumpmem command, but gdb itself has support for dumping memory regions. The verbose command is converted to the common --verbose flag since only two call sites use it now. Support for the clearstats command is dropped entirely, but no other sim really does this, and the same thing can be done by reloading. If it's important (clearing cycle stats) to someone, we can add a common function for it.
2015-04-17sim: replace CIA_{GET,SET} with CPU_PC_{GET,SET}Mike Frysinger64-116/+184
The CIA_{GET,SET} macros serve the same function as CPU_PC_{GET,SET} except the latter adds a layer of indirection via the sim state. This lets models set up different functions at runtime and doesn't reach so directly into the arch-specific cpu state. It also doesn't make sense to have two sets of macros that do exactly the same thing, so lets standardize on the one that gets us more.
2015-04-17sim: arm/cr16/d10v/h8300/microblaze/sh: fill out sim-cpu pc fetch/store helpersMike Frysinger13-0/+159
This makes the common sim-cpu logic work.
2015-04-16sim: avr/mcore/moxie: fill out sim-cpu pc fetch/store helpersMike Frysinger7-1/+80
This makes the common sim-cpu logic work.
2015-04-15sim: unify sim-cpu usageMike Frysinger69-139/+126
Now that all the targets are utilizing CPU_PC_{FETCH,STORE}, and the cpu state is multicore, and the STATE_CPU defines match, we can move it all to the common code.
2015-04-15sim: cris/frv/h8300/iq2000/lm32/m32r/sh64: standardize cpu stateMike Frysinger15-15/+88
This sets up the sim_state structure and the cpu member to match what we do in most other sims, and what the common code suggests. This is a step to unifying on the sim-cpu.o object.
2015-04-13sim: ppc: fix up version scriptMike Frysinger2-2/+8
The common sim code has switched to using gdb directly; update the ppc copy too.
2015-04-13sim: fix the PKGVERSION defineMike Frysinger55-55/+164
This should be SIM, not GDB.
2015-04-13sim: options: add --version supportMike Frysinger2-0/+18
The old run frontend had a --version option, but the new common sim-options file does not. Restore support for that so we can get version info out of `run` when using the new frontend.
2015-04-13sim: switch to gdb version scriptMike Frysinger3-40/+8
Since the local create-version.sh already points directly into the gdb source tree, we might as well use the gdb script directly too.
2015-04-13sim: mn10300: convert to sim-cpuMike Frysinger4-10/+47
Make cpu allocation fully dynamic so we can leverage the common sim-cpu and its APIs.
2015-04-13sim: v850: convert to sim-cpuMike Frysinger4-9/+42
Make cpu allocation fully dynamic so we can leverage the common sim-cpu and its APIs.
2015-04-13sim: mips: convert to sim-cpuMike Frysinger4-11/+44
Make cpu allocation fully dynamic so we can leverage the common sim-cpu and its APIs.
2015-04-13sim: m68hc11: convert to sim-cpuMike Frysinger4-11/+48
Make cpu allocation fully dynamic so we can leverage the common sim-cpu and its APIs.
2015-04-13sim: mips: fix prototype warningsMike Frysinger2-63/+43
Convert a bunch of old style prototypes and tweak various casts to match the function signatures.
2015-04-13sim: ft32: fix ft32_pc_get logicMike Frysinger2-1/+5
2015-04-13Do unset_currtarget_info ldscript for all simulator testsuites.Hans-Peter Nilsson4-6/+18
sim/testsuite: * sim-defs.exp (sim_init): Unset target ldscript here. sim/testsuite/sim/mips: * basic.exp: Don't unset target ldscript here.
2015-04-12sim: arm/mips: fix sim_read/sim_write linkage errorsMike Frysinger4-2/+11
With sim-hrw.o being built & linked in the common list, some people are getting linking errors now for these targets. Move the main objects that provide these functions before the common list to avoid that.
2015-04-12sim: ft32: delete sim_read/sim_write funcsMike Frysinger2-22/+4
The common sim-hrw.o provides both of these, so simply use them.
2015-04-06sim: move sim-engine.o/sim-hrw.o to the common listMike Frysinger46-35/+100
This makes these two objects available to all sims by default.
2015-04-05sim: moxie: fix running after nrun conversionMike Frysinger7-25/+102
The nrun conversion was slightly incorrect in how it stopped when an exception occurred. We still set cpu.asregs.exception, but nothing was checking it anymore. Convert all of that to sim_engine_halt. To keep things from regressing again, add a basic testsuite too.
2015-04-05sim: mn10300: add a basic testsuiteMike Frysinger4-0/+88
2015-04-05sim: m68hc11: add a basic testsuiteMike Frysinger4-0/+78
2015-04-05sim: iq2000: add a basic testsuiteMike Frysinger4-0/+78
2015-04-05sim: lm32: add a basic testsuiteMike Frysinger4-0/+84
2015-04-02sim: d10v: fix signal updatesMike Frysinger2-8/+11
Way back in aba6488e0b73756f31f154d12a228baa82a68d8a, a bunch of signal defines were changed to TARGET_SIGNAL_xxx. For d10v, the transition was incomplete which lead to sim_stop_reason using the new set but sim_resume still using the old set. Which meant in some cases, the sim would never actually stop. Convert all the remaining SIGxxx defines in here to TARGET_SIGNAL_xxx. This has the nice side effect of fixing the testsuite.
2015-04-02Regenerate configure in simH.J. Lu29-56/+88
* arm/configure: Regenerated. * avr/configure: Likewise. * bfin/configure: Likewise. * common/configure: Likewise. * cr16/configure: Likewise. * cris/configure: Likewise. * d10v/configure: Likewise. * erc32/configure: Likewise. * frv/configure: Likewise. * ft32/configure: Likewise. * h8300/configure: Likewise. * igen/configure: Likewise. * iq2000/configure: Likewise. * lm32/configure: Likewise. * m32c/configure: Likewise. * m32r/configure: Likewise. * m68hc11/configure: Likewise. * mcore/configure: Likewise. * microblaze/configure: Likewise. * mips/configure: Likewise. * mn10300/configure: Likewise. * moxie/configure: Likewise. * msp430/configure: Likewise. * ppc/configure: Likewise. * rl78/configure: Likewise. * rx/configure: Likewise. * sh/configure: Likewise. * sh64/configure: Likewise. * v850/configure: Likewise.
2015-04-02sim: clean up SIM_EXTRA_OBJS referencesMike Frysinger8-21/+33
This variable was deleted in previous commits and is not used anymore. Prune any stray references to it.
2015-04-01Fix sim buildH.J. Lu3-12/+14
* common/Make-common.in (CSEARCH): Remove $(ZLIBINC). (BFD_LIB): Remove $(ZLIB). (CONFIG_LIBS): Add $(ZLIB). * ppc/Makefile.in (ZLIBINC): Removed. (INCLUDES): Remove $(ZLIBINC). (BFD_LIB): Remove $(ZLIB).
2015-04-01Regenerate configure in simH.J. Lu30-111/+204
* arm/configure: Regenerated. * avr/configure: Likewise. * bfin/configure: Likewise. * common/configure: Likewise. * cr16/configure: Likewise. * cris/configure: Likewise. * d10v/configure: Likewise. * erc32/configure: Likewise. * frv/configure: Likewise. * ft32/configure: Likewise. * h8300/configure: Likewise. * igen/configure: Likewise. * iq2000/configure: Likewise. * lm32/configure: Likewise. * m32c/configure: Likewise. * m32r/configure: Likewise. * m68hc11/configure: Likewise. * mcore/configure: Likewise. * microblaze/configure: Likewise. * mips/configure: Likewise. * mn10300/configure: Likewise. * moxie/configure: Likewise. * msp430/configure: Likewise. * ppc/configure: Likewise. * rl78/configure: Likewise. * rx/configure: Likewise. * sh/configure: Likewise. * sh64/configure: Likewise. * v850/configure: Likewise.
2015-04-01sim: m32c: enable warnings & clean up a bunchMike Frysinger16-54/+208
This doesn't clean up all the warnings, just most of them. The ones that are left will require some care to unravel.
2015-04-01sim: run: punt!Mike Frysinger17-513/+32
Now that all targets have been converted to nrun, we can finally punt this old inconsistent interface. A few stray references to the old run were sprinkled about; clean them up in the process. We leave behind the run(1) man page mostly so that we get it updated for the new nrun interface.
2015-04-01sim: update zlib handlingMike Frysinger85-2441/+567
With zlib being mandatory, and the updated m4 configs, we need to regen and use the new settings w/bfd to avoid linkage errors.
2015-03-31sim: cr16/d10v: restore generated headers depMike Frysinger4-0/+12
While cleaning up stale make rules, one too many were deleted. The build system autogenerates static rules, but not generated files.
2015-03-31common: cgen-mem/cgen-ops: fix extern inline handlingMike Frysinger3-2/+9
With newer versions of gcc (5.x), the extern inline we're using with the cgen-{mem,ops} modules no longer work. Since this code really wants the gnu inline semantics, use that attribute explicitly.
2015-03-31sim: m68hc11: fix gcc-5 build error w/restrict keywordMike Frysinger3-8/+15
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