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AgeCommit message (Expand)AuthorFilesLines
1997-07-15Configure r5900 testsuite sub-directory.Andrew Cagney2-1/+38
1997-07-15Similistic configure/build scripts for tx59 simulator tests.Andrew Cagney5-0/+1182
1997-07-15Generic tests for 5900.Andrew Cagney2-0/+40
1997-07-14Standard simulator tests.Andrew Cagney4-0/+65
1997-07-11Tests for mips r5900 instructionsAndrew Cagney56-0/+892
1997-07-11Fix a number of problems in the r5900 specific p* (parallel) instructions.Andrew Cagney3-90/+177
1997-07-03Sync powerpc simulator with public version. Enable FPSCR and stringAndrew Cagney1-1/+1
1997-07-02 * gencode.c (build_instruction): Handle "pext5" according toJeff Law2-1/+4
1997-07-02 * gencode.c (build_instruction): Handle "ppac5" according toJeff Law2-1/+6
1997-07-02 * interp.c (sim_engine_run): Reset the ZERO register to zeroJeff Law2-23/+40
1997-07-02 * gencode.c (FEATURE_WARNINGS): Remove FEATURE_WARN_ZERO.Jeff Law2-3/+20
1997-06-27Add test for dbt/rtd instructionsAndrew Cagney1-0/+38
1997-06-24 * interp.c (sim_resume): Clear State.exited.Jeff Law1-0/+1
1997-06-12 * simops.c: Fix thinko in last change.Jeff Law2-1/+5
1997-06-10 * simops.c: "call" stores the callee saved registers into theJeff Law2-53/+55
1997-06-10 * simops.c: Fix return address computation for "call" instructions.Jeff Law2-2/+10
1997-06-06Open in binary mode when available.Andrew Cagney1-0/+8
1997-06-06Clean up formatting of instruction traces.Andrew Cagney1-0/+33
1997-06-05Verify magic number of simulator struct.Andrew Cagney1-0/+4
1997-06-04Initialize the sim-engine module.Andrew Cagney1-0/+12
1997-06-03o Fixes to repeated watchpointsAndrew Cagney3-110/+228
1997-06-02o Fix padd insnAndrew Cagney1-8/+12
1997-05-30Add assembler information to igen input files.Andrew Cagney7-153/+309
1997-05-29Fix subu immed - was incorrectly using unsigned.Andrew Cagney3-1/+10
1997-05-29Add a simple dissasembler to igenAndrew Cagney4-38/+740
1997-05-27Fix watching PC for 64bit (mips) target.Andrew Cagney2-42/+146
1997-05-27Extend xor-endian and per-cpu support in core module.Andrew Cagney11-63/+294
1997-05-23Preliminary suport for xor-endian suport in core module.Andrew Cagney6-79/+181
1997-05-23Incorrect test for zero-r0 code gen.Andrew Cagney2-2/+12
1997-05-23Enumerate longjmp's return type.Andrew Cagney1-0/+5
1997-05-22ifdef out uses of simSTOP, simSTEP and simBE when DEBUG is defined.Gavin Romig-Koch2-0/+9
1997-05-22Change longjmp param/setjmp return value used for simulator restart from 0 to 2.Gavin Romig-Koch3-6/+27
1997-05-22 * interp.c (sim_resume): Add missing case in big switchJeff Law2-0/+6
1997-05-21Watchpoint interface.Andrew Cagney16-817/+1486
1997-05-20 * interp.c: Replace all references to load_mem and store_memJeff Law3-340/+295
1997-05-20Part II of adding callback argument to sim_open(). Update all theAndrew Cagney7-56/+48
1997-05-20Depreciate sim_set_callbacks() function. Set simulator callbacksAndrew Cagney3-18/+19
1997-05-19Make getpid, kill supported system callsMichael Meissner6-39/+157
1997-05-19 * interp.c (dispatch): Make this an inline function.Jeff Law3-7/+10
1997-05-19Graft sim/common event and other code onto the mips simulator.Andrew Cagney5-220/+196
1997-05-19Update.Andrew Cagney1-3/+8
1997-05-19Make simulator event-queue manager a bit more signal safe.Andrew Cagney3-0/+26
1997-05-19o Implement generic halt/restart/abort module.Andrew Cagney18-368/+1406
1997-05-19Pacify gcc.Andrew Cagney1-0/+4
1997-05-18 * interp.c (load_mem_big): Remove function. It's now a macroJeff Law2-26/+34
1997-05-17Treat infinities like normal numbers for purposes of comparisonsMichael Meissner2-6/+11
1997-05-16 * callback.c (os_close): Mark the descriptor as beingJeff Law2-6/+127
1997-05-16 * interp.c (load_mem): If we get a load from an out of rangeJeff Law2-0/+18
1997-05-16o Make tic80 insn file more `cache ready'Andrew Cagney9-174/+218
1997-05-15Remove some of the flake from the c80 floating point.Andrew Cagney5-50/+617
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