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2015-11-15sim: cr16: delete unused memory helpersMike Frysinger3-20/+6
These aren't used anywhere and are just leftover from the d10v port. Delete them so follow up commits are easier to follow.
2015-11-15sim: cr16: switch to common sim-regMike Frysinger3-13/+61
This is mostly to get us off the weird cr16 specific memory functions, but it's also a good clean up to move to the common core.
2015-11-15sim: cr16/d10v: drop redundant call to sim_create_inferiorMike Frysinger4-2/+8
With the conversion to the nrun frontend, this call should no longer be necessary. It also actively crashes when trying to use the sd state.
2015-11-15sim: d10v: drop global callback stateMike Frysinger4-137/+149
Now that we have access to the sim state in all the right places, use existing sim helpers in place of d10v_callback directly.
2015-11-15sim: d10v: convert to common sim engine logicMike Frysinger5-218/+137
Now that we have access to the sim state everywhere, we can convert to the common engine logic for overall processing. This frees us up from tracking exception state ourselves.
2015-11-15sim: d10v: push down sd/cpu varsMike Frysinger6-500/+543
By itself, this commit doesn't really change anything. It lays the groundwork for using the cpu state in follow up commits, both for engine state and for cpu state. Splitting things up this way so it is easier to see how things have changed.
2015-11-15sim: h8300: convert to common sim_{reason,stop}Mike Frysinger3-15/+8
This ends up being pretty easy as the h8300 port already supports much of the common engine core.
2015-11-15sim: mcore: pull cpu state out of global scopeMike Frysinger3-294/+309
This avoids using global variables to hold the cpu state so we can better integrate with the sim common code. There's also a minor fix here where we move the pc register back into the state that is accessible by the asints array. When it was pulled out previously, the reg store/fetch functions broke, but no one really noticed as the mcore gdb port was dropped a while back.
2015-11-15sim: mcore: switch to common sim-regMike Frysinger3-4/+16
This is not entirely useful as mcore doesn't (yet) store its register state in the cpu state, but it does allow for switching to the common code for these functions.
2015-11-15sim: mcore: add a fail testcaseMike Frysinger3-1/+14
2015-11-15sim: mcore: convert to common reason/resume logicMike Frysinger3-40/+64
Switch over to the common event loop logic so we don't have to maintain the exception/exit logic ourselves.
2015-11-15sim: clean up redundant objectsMike Frysinger8-20/+19
Some of the target makefiles listed objects that were already pulled in via SIM_NEW_COMMON_OBJS. Clean those up.
2015-11-15sim: sim-close: unify sim_close logicMike Frysinger50-171/+173
Other than the nice advantage of all sims having to declare one fewer common function, this also fixes leakage in pretty much every sim. Many were not freeing any resources, and a few were inconsistent as to the ones they did. Now we have a single module that takes care of all the logic for us. Most of the non-cgen based ones could be deleted outright. The cgen ones required adding a callback to the arch-specific cleanup func. The few that still have close callbacks are to manage their internal state. We do not convert erc32, m32c, ppc, rl78, or rx as they do not use the common sim core.
2015-11-15sim: m32c: add a basic testsuiteMike Frysinger5-0/+92
2015-11-15sim: testsuite: support basic vars in flagsMike Frysinger2-1/+12
Sometimes in tests, we need supplemental files like linker scripts or board helper files. There's no way to set those flags in the tests currently and relative paths don't work (breaks out of tree builds). Update the main option parser to replace some strings on the fly. Now tests can do things like: Long term we'll want to switch the framework to use the dejagnu helpers like dg-xxx that gcc & gdb utilize. But that'll require more rework.
2015-11-10Update the RX simulator to handle the latest opcode types.Nick Clifton2-1/+24
* rx.c (id_names): Add nop4, nop5, nop6 and nop7. (decode_opcode): Likewise. (get_op): Handle RX_Operand_Zero_Indirect. Handle RX_Bad_Size and RX_MAX_SIZE. (put_op): Likewise. (N_MAP): Increase to 90.
2015-11-10sim: cr16/d10v: localize translation funcsMike Frysinger4-6/+18
These functions are only used in the interp module, so there's no point in exporting them and declaring them in the external sim interface.
2015-11-10sim: m32c: move test code to testsuiteMike Frysinger8-26/+17
Various target code belongs in the testsuite/ subdir, so move the m32c code to match all the other targets.
2015-11-10sim: m32c: drop redundant dependency infoMike Frysinger2-13/+4
2015-11-10sim: h8300: drop unused littleendian variableMike Frysinger2-13/+5
2015-10-12sim: ft32: test coverage for link parameters and PM write portJames Bowman2-0/+42
Adds test coverage for recent features.
2015-10-11sim: moxie: fix leakage in error path [BZ #18273]Mike Frysinger2-0/+6
Reported-by: dcb <dcb314@hotmail.com>
2015-10-11sim: bfin: handle negative left saturated shifts as ashifts [BZ #18407]Mike Frysinger4-1/+33
When handling left saturated ashifts with negative immediates, they should be treated as right ashifts. This matches hardware behavior. Reported-by: Igor Rayak <igorr@gitatechnologies.com>
2015-09-29sim: ft32: correct simulation of MEMCPY and MEMSETJames Bowman2-2/+7
The MEMCPY and MEMSET instructions should only examine the low 15 bits of their length arguments.
2015-09-29sim: ft32: correctly simulate PM write portJames Bowman2-2/+10
The FT32 simulator was not correctly simulating the behavior of the program memory (PM) write port. When it is locked, writes to the data register do nothing.
2015-09-25[PATCH] Add micromips support to the MIPS simulatorAndrew Bennett22-1468/+7290
2015-09-25 Andrew Bennett <andrew.bennett@imgtec.com> Ali Lown <ali.lown@imgtec.com> sim/common/ * sim-bits.h (EXTEND6): New macro. (EXTEND12): New macro. (EXTEND25): New macro. sim/mips/ * Makefile.in (tmp-micromips): New rule. (tmp-mach-multi): Add support for micromips. * configure.ac (mips*-sde-elf* | mips*-mti-elf*): Made a multi sim that works for both mips64 and micromips64. (mipsisa32r2*-*-*): Made a multi sim that works for mips32 and micromips32. Add build support for micromips. * dsp.igen (do_ph_s_absq, do_w_s_absq, do_qb_s_absq, do_addsc, do_addwc, do_bitrev, do_extpv, do_extrv, do_extrv_s_h, do_insv, do_lxx do_modsub, do_mthlip, do_mulsaq_s_w_ph, do_ph_packrl, do_qb_pick do_ph_pick, do_qb_ph_precequ, do_qb_ph_preceu, do_w_preceq do_w_ph_precrq, do_ph_qb_precrq, do_w_ph_rs_precrq do_qb_w_raddu, do_rddsp, do_repl, do_shilov, do_ph_shl, do_qb_shl do_w_s_shllv, do_ph_shrlv, do_w_r_shrav, do_wrdsp, do_qb_shrav, do_append, do_balign, do_ph_w_mulsa, do_ph_qb_precr, do_prepend): New functions. Refactored instruction code to use these functions. * dsp2.igen: Refactored instruction code to use the new functions. * interp.c (decode_coproc): Refactored to work with any instruction encoding. (isa_mode): New variable (RSVD_INSTRUCTION): Changed to 0x00000039. * m16.igen (BREAK16): Refactored instruction to use do_break16. (JALX32): Add mips32, mips64, mips32r2 and mips64r2 models. * micromips.dc: New file. * micromips.igen: New file. * micromips16.dc: New file. * micromipsdsp.igen: New file. * micromipsrun.c: New file. * mips.igen (do_swc1): Changed to work with any instruction encoding. (do_add do_addi do_andi do_dadd do_daddi do_dsll32 do_dsra32 do_dsrl32, do_dsub, do_break, do_break16, do_clo, do_clz, do_dclo do_dclz, do_lb, do_lh, do_lwr, do_lwl, do_lwc, do_lw, do_lwu, do_lhu do_ldc, do_lbu, do_ll, do_lld, do_lui, do_madd, do_dsp_madd, do_maddu do_dsp_maddu, do_dsp_mfhi, do_dsp_mflo, do_movn, do_movz, do_msub do_dsp_msub, do_msubu, do_dsp_msubu, do_mthi, do_dsp_mthi, do_mtlo do_dsp_mtlo, do_mul, do_dsp_mult, do_dsp_multu, do_pref, do_sc, do_scd do_sub, do_sw, do_teq, do_teqi, do_tge, do_tgei, do_tgeiu, do_tgeu, do_tlt do_tlti, do_tltiu, do_tltu, do_tne, do_tnei, do_abs_fmt, do_add_fmt do_alnv_ps, do_c_cond_fmt, do_ceil_fmt, do_cfc1, do_ctc1, do_cvt_d_fmt do_cvt_l_fmt, do_cvt_ps_s, do_cvt_s_fmt, do_cvt_s_pl, do_cvt_s_pu do_cvt_w_fmt, do_div_fmt, do_dmfc1b, do_dmtc1b, do_floor_fmt, do_luxc1_32 do_luxc1_64, do_lwc1, do_lwxc1, do_madd_fmt, do_mfc1b, do_mov_fmt, do_movtf do_movtf_fmt, do_movn_fmt, do_movz_fmt, do_msub_fmt, do_mtc1b, do_mul_fmt do_neg_fmt, do_nmadd_fmt, do_nmsub_fmt, do_pll_ps, do_plu_ps, do_pul_ps do_puu_ps, do_recip_fmt, do_round_fmt, do_rsqrt_fmt, do_prefx, do_sdc1 do_suxc1_32, do_suxc1_64, do_sqrt_fmt, do_sub_fmt, do_swc1, do_swxc1 do_trunc_fmt): New functions, refactored from existing instructions. Refactored instruction code to use these functions. (RSVD): Changed to use new reserved instruction. (loadstore_ea, not_word_value, unpredictable, check_mt_hilo, check_mf_hilo, check_mult_hilo, check_div_hilo, check_u64, do_luxc1_32, do_sdc1, do_suxc1_32, check_fmt_p, check_fpu, do_load_double, do_store_double): Added micromips32 and micromips64 models. Added include for micromips.igen and micromipsdsp.igen Add micromips32 and micromips64 models. (DecodeCoproc): Updated to use new macro definition. * mips3264r2.igen (do_dsbh, do_dshd, do_dext, do_dextm, do_dextu, do_di, do_dins, do_dinsm, do_ei, do_ext, do_mfhc1, do_mthc1, do_ins, do_dinsu, do_seb, do_seh do_rdhwr, do_wsbh): New functions. Refactored instruction code to use these functions. * sim-main.h (CP0_operation): New enum. (DecodeCoproc): Updated macro. (IMEM32_MICROMIPS, IMEM16_MICROMIPS, MICROMIPS_MINOR_OPCODE, MICROMIPS_DELAYSLOT_SIZE_ANY, MICROMIPS_DELAYSLOT_SIZE_16, MICROMIPS_DELAYSLOT_SIZE_32, ISA_MODE_MIPS32 and ISA_MODE_MICROMIPS): New defines. (sim_state): Add isa_mode field. sim/testsuite/sim/mips/ * basic.exp (run_micromips_test, run_sim_tests): New functions Add support for micromips tests. * hilo-hazard-4.s: New file. * testutils.inc (_dowrite): Changed reserved instruction encoding. (writemsg): Moved the la and li instructions before the data they are assigned to, which prevents a bug where MIPS32 relocations are used instead of micromips relocations when building for micromips.
2015-09-22sim: ft32: add character input portJames Bowman2-0/+6
The FT32 simulator has character output, of course. This patch adds character input, which lets the simulator run interactive FT32 applications, e.g. language interpreters.
2015-08-05Fix building GDB for the M32C by providing a stub sim_info function.Nick Clifton2-0/+11
* gdb-if.c (sim_info): Stub function to allow GDB to be built with this simulator.
2015-07-24Remove leading/trailing white spaces in ChangeLogH.J. Lu31-1219/+1219
2015-07-14Remove extraneous whitespace from ARM sim sources.Nick Clifton29-320/+348
* armcopro.c: Remove extraneous whitespace. * armdefs.h: Likewise. * armfpe.h: Likewise. * arminit.c: Likewise. * armopts.h: Likewise. * armos.c: Likewise. * armos.h: Likewise. * armrdi.c: Likewise. * armsupp.c: Likewise. * armvirt.c: Likewise. * bag.c: Likewise. * bag.h: Likewise. * communicate.c: Likewise. * communicate.h: Likewise. * dbg_conf.h: Likewise. * dbg_cp.h: Likewise. * dbg_hif.h: Likewise. * dbg_rdi.h: Likewise. * gdbhost.c: Likewise. * gdbhost.h: Likewise. * iwmmxt.c: Likewise. * iwmmxt.h: Likewise. * kid.c: Likewise. * main.c: Likewise. * maverick.c: Likewise. * parent.c: Likewise. * thumbemu.c: Likewise. * wrapper.c: Likewise.
2015-07-02Fix snafu with latest addition to the ARM sim.Nick Clifton2-1/+7
* Makefile.in (SIM_EXTRA_CFLAGS): Revert previous delta. (SIM_EXTRA_LIBS): Add -lm.
2015-06-28Add support for ARM v6 instructions.Nick Clifton9-126/+3881
* Makefile.in (SIM_EXTRA_CFLAGS): Add -lm. * armdefs.h (ARMdval, ARMfval): New types. (ARM_VFP_reg): New union. (struct ARMul_State): Add VFP_Reg and FPSCR fields. (VFP_fval, VFP_uword, VFP_sword, VFP_dval, VFP_dword): Accessor macros for the new VFP_Reg field. * armemu.c (handle_v6_insn): Add code to handle MOVW, MOVT, QADD16, QASX, QSAX, QSUB16, QADD8, QSUB8, UADD16, USUB16, UADD8, USUB8, SEL, REV, REV16, RBIT, BFC, BFI, SBFX and UBFX instructions. (handle_VFP_move): New function. (ARMul_Emulate16): Add checks for newly supported v6 instructions. Add support for VMRS, VMOV and MRC instructions. (Multiply64): Allow nRdHi == nRm and/or nRdLo == nRm when operating in v6 mode. * armemu.h (t_resolved): Define. * armsupp.c: Include math.h. (handle_VFP_xfer): New function. Handles VMOV, VSTM, VSTR, VPUSH, VSTM, VLDM and VPOP instructions. (ARMul_LDC): Test for co-processor 10 or 11 and pass call to the new handle_VFP_xfer function. (ARMul_STC): Likewise. (handle_VFP_op): New function. Handles VMLA, VMLS, VNMLA, VNMLS, VNMUL, VMUL, VADD, VSUB, VDIV, VMOV, VABS, VNEG, VSQRT, VCMP, VCMPE and VCVT instructions. (ARMul_CDP): Test for co-processor 10 or 11 and pass call to the new handle_VFP_op function. * thumbemu.c (tBIT, tBITS, ntBIT, ntBITS): New macros. (test_cond): New function. Tests a condition and returns non-zero if the condition has been met. (handle_IT_block): New function. (in_IT_block): New function. (IT_block_allow): New function. (ThumbExpandImm): New function. (handle_T2_insn): New function. Handles T2 thumb instructions. (handle_v6_thumb_insn): Add next_instr and pc parameters. (ARMul_ThumbDecode): Add support for IT blocks. Add support for v6 instructions. * wrapper.c (sim_create_inferior): Detect a thumb address and call SETT appropriately.
2015-06-24sim: trace: drop unused trace_one_insnMike Frysinger3-98/+5
Everyone has migrated to the split functions (trace_prefix + trace_generic) a while ago, so we can drop this one now.
2015-06-24sim: trace: rename debug_printf fullyMike Frysinger3-5/+10
Rather than redirect using a define, just rename the symbol fully.
2015-06-24sim: trace: add a basic cpu register classMike Frysinger8-42/+56
The bfin/msp430 ports already had trace logic set up for reading/writing cpu registers, albeit using different unrelated levels (core & vpu). Add a proper register class for these and for other ports.
2015-06-24sim: trace: add set of system helpersMike Frysinger2-0/+28
Some code paths trace on a system instance and not a cpu instance (like the events code), so add some helpers for those cases.
2015-06-24sim: trace: document alu/fpu/vpu trace options betterMike Frysinger3-7/+14
Make the acronyms clear for people.
2015-06-23sim: common: replace SIM_FILTER_PATH with lbasenameMike Frysinger3-26/+16
This helper macro has largely the same behavior as libiberty's lbasename. There is a slight nuance related to colons, but it's not clear what the point of that is, and the code implies that it just wants the basename.
2015-06-23sim: use AS_HELP_STRING everywhereMike Frysinger60-368/+791
This helps standardize the configure --help output.
2015-06-23sim: trace: do not enable internal debug by defaultMike Frysinger2-2/+6
Since --trace-debug is for people hacking on the sim sources rather than people just using the sim, default it to off. This matches the behavior of other debug knobs we have.
2015-06-23sim: assume recentish compiler/systemsMike Frysinger6-43/+14
Assume the build system supports stdint.h/stdarg.h as those have been around long enough and we don't care about pre-stdc compilers anymore.
2015-06-21sim: common: add basic model assertMike Frysinger2-0/+5
If the configured in default doesn't match a known value, throw an assertion failure rather than segfaulting deeper down.
2015-06-21sim: common: use standard intXX_t types for signedXXMike Frysinger2-82/+27
Let's assume that the system supports the POSIX int8/16/32/64_t types as this collapses the logic significantly.
2015-06-21sim: common: standardize multiple include definesMike Frysinger6-13/+26
We use SIM_xxx_H in most headers, so convert _SIM_xxx_H_ over to it.
2015-06-18sim: syscall: simplify unknown syscall traceMike Frysinger2-5/+7
Since we always include the raw syscall number when tracing, also including it in the name when it's unknown is redundant. Simplify the code by using a constant string.
2015-06-18sim: callback: fix sentinel testing when walking mapsMike Frysinger2-2/+7
The new helpers for walking the maps tested the wrong value for exiting the for loop. This caused crashes when looking up entries that were not in the map.
2015-06-17sim: syscall: add common sim_syscall helpersMike Frysinger15-171/+197
Many ports have the same sim syscall logic, so add some helpers to handle all the common details. The arches still have to deal with the unpacking and packing of the syscall arguments, but the rest of the sim<->callback glue is now shared.
2015-06-17sim: syscall: unify memory helpersMike Frysinger20-214/+167
Almost every port implements these two callbacks in the same way, so unify them in the common layer.
2015-06-17sim: callback: add human readable strings for debugging to mapsMike Frysinger7-675/+768
When tracing, we often want to display the human readable name for the various syscall/errno values. Rather than make each target duplicate the lookup, extend the existing maps to include the string directly, and add helper functions to look up the constants. While most targets are autogenerated (from libgloss), the bfin/cris targets have custom maps for the Linux ABI which need to be updated by hand.
2015-06-12sim: bfin: expand CB_SYS_xxx commentMike Frysinger2-1/+7