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2001-08-02Removed a section of code that didn't do anything, but left values inJohn R. Moore2-19/+5
memory. This was labeled as a hack to set r0/r1 with argc/argv.
2001-07-312001-07-31 Ben Elliston <bje@redhat.com>Ben Elliston2-6/+12
* lib/sim-defs.exp (run_sim_test): Include a description such as "assembling" or "linking" that identifies the phase a test fails in, for easier analysis of failures.
2001-07-28 * dv-m68hc11eepr.c (m68hc11eepr_info): Fix print of current writeStephane Carrez2-5/+11
address. (m68hc11eepr_port_event): Fix detach/attach logic.
2001-07-22 * Makefile.in (SIM_OBJS): Remove sim-resume.oStephane Carrez3-1/+88
* interp.c (sim_resume): New function from sim-resume.c, install the stepping event after having processed the pending ticks. (has_stepped): Likewise. (sim_info): Produce an output only if verbose or STATE_VERBOSE_P.
2001-07-18Regenerate using autoconf 2.13.Andrew Cagney2-29/+105
2001-07-16Makefile.in: Add dependencies on $(CPU_H).Daniel Jacobowitz2-3/+7
2001-07-10* Makefile.in (gencode): Provide explicit path to gencode.c.Andrew Cagney2-1/+5
2001-07-052001-07-05 Ben Elliston <bje@redhat.com>Ben Elliston8-15/+42
* Make-common.in (srccgen): Remove. (CGEN_CPU_DIR): Define. (CGEN_READ_SCM): Redefine without $(srccgen). (CGEN_ARCH_SCM): Ditto. (CGEN_CPU_SCM): Ditto. (CGEN_DECODE_SCM): Ditto. (CGEN_DESC_SCM): Ditto. * $arch/Makefile.in: Use $(CGEN_CPU_DIR) where applicable.
2001-05-20Improve HC11 simulator to support HC12Stephane Carrez6-201/+1710
2001-05-20 * dv-m68hc11sio.c (m68hc11sio_tx_poll): Always check forStephane Carrez4-23/+63
pending interrupts. * interrupts.c (interrupts_process): Keep track of the last number of masked insn cycles. (interrupts_initialize): Clear last number of masked insn cycles. (interrupts_info): Report them. (interrupts_update_pending): Compute clear and set masks of interrupts and clear the interrupt bits before setting them (due to SCI interrupt sharing). * interrupts.h (struct interrupts): New members last_mask_cycles and xirq_last_mask_cycles.
2001-05-11Fix handling of XScale LDRD and STRD instructions with post indexed ↵Nick Clifton2-6/+11
addressing modes.
2001-05-10Don't loose last block during a dma.Andrew Cagney2-1/+6
2001-05-08Check Mode not Bank in order to determine rocesor mode.Nick Clifton2-1/+7
2001-05-07*** empty log message ***Jim Blandy1-0/+4
2001-05-07* mn10300.igen: Doc fixes.Jim Blandy1-6/+6
2001-04-26* Makefile.in (idecode.o, op_utils.o, semantics.o, simops.o):Alexandre Oliva2-2/+7
Depend on targ-vals.h.
2001-04-25* thanks, nickcFrank Ch. Eigler3-0/+9
2001-04-25 Frank Ch. Eigler <fche@redhat.com> * sim-load.c (sim_load_file): Put it back [...]
2001-04-21Revert call to bfd_cache_close().Andrew Cagney3-4/+6
2001-04-19* bug fixFrank Ch. Eigler3-0/+10
2001-04-19 Frank Ch. Eigler <fche@redhat.com> * sim-utils.c (sim_analyze_program): Call bfd_cache_close after we're finished with its immediate use. * sim-load.c (sim_load_file): Ditto.
2001-04-18* XScale coprocessor support.Matthew Green6-22/+284
2001-04-18 matthew green <mrg@redhat.com> * armcopro.c (write_cp15_reg): Set CHANGEMODE if endianness changes. (read_cp15_reg): Make non-static. (XScale_cp15_LDC): Update for write_cp15_reg() change. (XScale_cp15_MCR): Likewise. (XScale_cp15_write_reg): Likewise. (XScale_check_memacc): New function. Check for breakpoints being activated by memory accesses. Does not support the Branch Target Buffer. (XScale_set_fsr_far): New function. Set FSR and FAR for XScale. (XScale_debug_moe): New function. Set the debug Method Of Entry, if configured. (write_cp14_reg): Reset count counter if requested. * armdefs.h (struct ARMul_State): New members `LastTime' and `CP14R0_CCD' used for the timer/counters. (ARMul_CP13_R0_FIQ, ARMul_CP13_R0_IRQ, ARMul_CP13_R8_PMUS, ARMul_CP14_R0_ENABLE, ARMul_CP14_R0_CLKRST, ARMul_CP14_R0_CCD, ARMul_CP14_R0_INTEN0, ARMul_CP14_R0_INTEN1, ARMul_CP14_R0_INTEN2, ARMul_CP14_R0_FLAG0, ARMul_CP14_R0_FLAG1, ARMul_CP14_R0_FLAG2, ARMul_CP14_R10_MOE_IB, ARMul_CP14_R10_MOE_DB, ARMul_CP14_R10_MOE_BT, ARMul_CP15_R1_ENDIAN, ARMul_CP15_R1_ALIGN, ARMul_CP15_R5_X, ARMul_CP15_R5_ST_ALIGN, ARMul_CP15_R5_IMPRE, ARMul_CP15_R5_MMU_EXCPT, ARMul_CP15_DBCON_M, ARMul_CP15_DBCON_E1, ARMul_CP15_DBCON_E0): New defines for XScale registers. (XScale_check_memacc, XScale_set_fsr_far, XScale_debug_moe): Prototype. (ARMul_Emulate32, ARMul_Emulate26): Clean up function definition. (ARMul_Emulate32): Handle the clock counter and hardware instruction breakpoints. Call XScale_set_fsr_far() for software breakpoints and software interrupts. (LoadMult): Call XScale_set_fsr_far() for data aborts. (LoadSMult): Likewise. (StoreMult): Likewise. (StoreSMult): Likewise. * armemu.h (write_cp15_reg): Update prototype. * arminit.c (ARMul_NewState): Initialise CP14R0_CCD and LastTime. (ARMul_Abort): If XScale, check for FIQ and IRQ being enabled in CP13 register 0. * armvirt.c (GetWord): Call XScale_check_memacc(). (PutWord): Likewise.
2001-04-15* Makefile.in (simops.o): Add simops.h to dependency list.J.T. Conklin8-4/+20
2001-04-12* mips.igen (CFC1, CTC1): Pass the correct register numbers toJim Blandy3-4/+12
PENDING_FILL. Use PENDING_SCHED directly to handle the pending set of the FCSR. * sim-main.h (COCIDX): Remove definition; this isn't supported by PENDING_FILL, and you can get the intended effect gracefully by calling PENDING_SCHED directly.
2001-03-20Do not enable alignment checking when loading unaligned thumb instructions.Nick Clifton2-2/+7
2001-03-20* mmap support for common simulatorsFrank Ch. Eigler6-12/+205
2001-03-16 Frank Ch. Eigler <fche@redhat.com> Add support for mmap-based memory regions. * sim-memopt.c (mmap_next_fd): New global. (sim_memory_init): Reinitialize it. (OPTION_MEMORY_MAPFILE, memory_option_handler): Support new "--memory-mapfile FILE" option. Check for some errors. (do_memopt_add): Conditionally do mmap instead of malloc for backing store of simulated memory. Check for more errors. (do_simopt_delete, sim_memory_uninstall): Corresponding cleanup. * sim-memopt.h (munmap_length): New member of _sim_memopt. * configure.in: Look for mmap/fstat related functions and headers. * config.in, configure: Regenerated.
2001-03-16* tweakFrank Ch. Eigler2-3/+8
2001-03-15 Frank Ch. Eigler <fche@redhat.com> * sim-core.c (sim_core_map_attach): Correct overlap-related error messages.
2001-03-14Link with libintl, needed by libopcodes.Andrew Cagney2-2/+6
2001-03-07Remove reference to alloca-conf.hMichael Meissner2-2/+4
2001-03-06Fix BLX(1) for ThumbNick Clifton2-5/+24
2001-03-05Fixes for NetBSD 1.5. NetBSD has been renumbering/renaming itsAndrew Cagney2-0/+22
SYS_* interfaces.
2001-03-052001-03-05 Dave Brolley <brolleyDave Brolley17-635/+413
arch.c: Regenerate. arch.h: Regenerate. cpu.c: Regenerate. cpu.h: Regenerate. cpuall.h: Regenerate. cpux.c: Regenerate. cpux.h: Regenerate. decode.c: Regenerate. decode.h: Regenerate. decodex.c: Regenerate. decodex.h: Regenerate. model.c: Regenerate. modelx.c: Regenerate. sem-switch.c: Regenerate. sem.c: Regenerate. semx-switch.c: Regenerate.
2001-03-052001-03-05 Dave Brolley <brolley@Dave Brolley11-580/+336
* arch.c: Regenerate. * arch.h: Regenerate. * cpu.c: Regenerate. * cpu.h: Regenerate. * cpuall.h: Regenerate. * decode.c: Regenerate. * decode.h: Regenerate. * model.c: Regenerate. * sem-switch.c: Regenerate. * sem.c: Regenerate.
2001-02-28Add support for disabling alignment checks when performing GDB interfaceNick Clifton8-44/+95
calls or SWI emulaiton routines. (Alignment checking code has not yet been contributed).
2001-02-242001-02-23 Ben Elliston <bje@redhat.com>Ben Elliston2-0/+7
* sim-main.h (ENGINE_ISSUE_PREFIX_HOOK): Only define if not already defined elsewhere.
2001-02-222001-02-22 Ben Elliston <bje@redhat.com>Ben Elliston3-6/+35
* sim-trace.h (TRACE_VPU_IDX): Add. (TRACE_vpu): Define. (WITH_TRACE_VPU_P): Likewise. (TRACE_VPU_P): Likewise. * sim-trace.c (OPTION_TRACE_VPU): Define. (trace_options): Add --trace-vpu. (trace_option_handler): Handle OPTION_TRACE_VPU. (trace_option_handler): Include VPU tracing in --trace-semantics. (trace_idx_to_str): Handle TRACE_VPU_IDX.
2001-02-212001-02-21 Ben Elliston <bje@redhat.com>Ben Elliston2-2/+20
* sim-trace.h (TRACE_BRANCH_INPUT1): New macro. (TRACE_BRANCH_INPUT2): Likewise.
2001-02-192001-02-19 Ben Elliston <bje@redhat.com>Ben Elliston3-7/+15
* sim-main.h (sim_monitor): Return an int. * interp.c (sim_monitor): Add return values. (signal_exception): Handle error conditions from sim_monitor.
2001-02-16Remove Prefetch abort for breakpoints. Instead set the state to RESUME.Nick Clifton2-12/+7
2001-02-152001-02-16 Ben Elliston <bje@redhat.com>Ben Elliston2-1/+6
* MAINTAINERS: Add myself for common portions.
2001-02-15* profiling bug fixes.Ben Elliston2-2/+17
2001-02-09 Ben Elliston <bje@redhat.com> * (profile_print_pc): Write header out in target byte order. 2001-02-09 Ben Elliston <bje@redhat.com> * sim-profile.c (profile_pc_init): Correct bug in loop logic when adjusting the pc shift value.
2001-02-15Add code to preserve processor mode when a prefetchNick Clifton2-0/+14
abort is signalled after processing a breakpoint.
2001-02-14Reset processor into ARM mode for any machine type except the early ARMs.Nick Clifton2-12/+20
2001-02-14remove spurious whitespaceNick Clifton1-6/+6
2001-02-14Prevent Aborts from happening whilst emulating a SWINick Clifton2-62/+83
2001-02-12Fix definition of NEGBRANCHNick Clifton2-1/+6
2001-02-082001-02-08 Ben Elliston <bje@redhat.com>Chris Demetriou2-34/+23
* sim-main.c (load_memory): Pass cia to sim_core_read* functions. (store_memory): Likewise, pass cia to sim_core_write*.
2001-02-07* i960-desc.c: Update all the A macro definitions to the newDJ Delorie2-6/+31
stdc-sensitive versions that cgen would have used.
2001-02-01Add parentheses ready for future conbtributionNick Clifton1-39/+63
2001-02-01Update base address register after restoring register bank.Nick Clifton2-26/+64
2001-02-01 * Makefile.in (gencode): Link with libopcodes in build tree ratherJonathan Larmour2-4/+7
than building source files from there.
2001-02-01Detect installation of SWI vector by running program as well as loading program.Nick Clifton5-7/+18
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