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2011-05-16sim: tests: support .S/.c filesMike Frysinger2-9/+47
Rather than requiring all sim tests to be preprocessed .s files, add support for .S and .c files so we can easily write code using a higher level language like C. Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2011-05-14sim: bfin: allow pushing of SPMike Frysinger2-2/+6
The hardware respects this insn, and some code (like the on-chip bootrom) uses it, so allow it. Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2011-05-14sim: bfin: implement loop back support in the UARTsMike Frysinger4-23/+62
The UART has a LOOP_ENA bit in its MCR register where writes to the THR go to the RBR. Implement support for this mode. Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2011-05-11sim: fix func call style (space before paren)Mike Frysinger24-241/+250
Committed this as obvious: -foo(...); +foo (...); Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2011-05-11 PR sim/12737Hans-Peter Nilsson5-0/+11
* sim/arm/iwmmxt/wcmpgt.cgs, sim/arm/iwmmxt/wmac.cgs, sim/arm/iwmmxt/wsra.cgs, sim/arm/xscale/blx.cgs: Kfail.
2011-05-09sim: bfin: fix UART LSR read-only bit saturationMike Frysinger2-0/+6
A few bits in the newer UART LSR register are not sticky, so make sure we clear them when returning updated status rather than leaving them always set. Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2011-05-04gdb:Joseph Myers10-9/+29
* configure.host (xscale*): Don't handle target. * configure.tgt (thumb*-*-* | strongarm*-*-* | xscale-*-*): Don't handle targets. gdb/gdbserver: * README: Don't mention xscale*-*-linux*. * configure.srv (xscale*-*-linux*): Don't handle target. gdb/testsuite: * gdb.base/a2-run.exp (strongarm-*-coff): Don't handle target. * gdb.base/float.exp (xscale*-*-*, strongarm*-*-*): Don't handle targets. * gdb.base/long_long.exp (xscale*-*-*, strongarm*-*-*): Don't handle targets. sim: * configure.tgt (thumb*-*-* | strongarm*-*-* | xscale-*-*): Don't handle targets. * configure: Regenerate. sim/testsuite: * configure: Regenerate. * sim/arm/allinsn.exp (xscale*-*-*): Don't handle target. * sim/arm/misc.exp (thumb*-*-*, xscale*-*-*): Don't handle targets. * sim/arm/iwmmxt/iwmmxt.exp: Test for arm*-*-* instead of xscale*-*-*. * sim/arm/thumb/allthumb.exp (thumb*-*-*): Don't handle target. * sim/arm/xscale/xscale.exp: Test for arm*-*-* instead of xscale*-*-*.
2011-04-27sim: bfin: constify dmac pmap arraysMike Frysinger2-13/+22
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2011-04-26sim: gpio: add output supportMike Frysinger2-16/+53
Make all of the pins bidirectional, and support sending signals when software drives the pins as outputs. Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2011-04-26sim: gpio: update mask a/b signals betterMike Frysinger2-12/+49
When the mask a/b MMRs are written, the output signal might change levels (as pins are [un]masked), so make sure we update the output level. Further, make sure we handle edge ints correctly by first sending a high signal followed by a low signal. Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2011-04-16sim: add sim_complete_command stubs for non-common-using portsMike Frysinger14-0/+69
For the ports that don't use the common/ subdir, we need to add stub funcs to them to avoid build failures with gdb and command completion. These do not implement the actual completion functionality ... any port that wants that can either convert to the common/ subdir, or fill out the function on their own time. Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2011-04-16sim: bfin: use store buffer with more 32bit insnsMike Frysinger2-23/+37
A bunch of 32bit insns were not using the store buffer, so when they were used in parallel insns, they would incorrectly clobber a register early. Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2011-04-15gdb: sim: add style fixes lost between git->cvsMike Frysinger1-0/+1
2011-04-15gdb: sim: add command line completionMike Frysinger2-0/+56
For now, only the sub-command name is completed. No support yet for completing options to that command. But even this is a huge step as currently, nothing is completed, and the basic "help sim" is fairly obtuse as to what exactly the "sim" command accepts. Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2011-04-15sim: bfin: handle implicit DISALGNEXCPT with video insnsMike Frysinger2-0/+30
When most video related insns are used in parallel with Ireg loads, the DISALGNEXCPT insn behavior is implicitly in effect. Reported-by: Anton Shokurov <shokurov.anton.v@yandex.ru> Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2011-04-11sim: bfin: respect the port level on signals to the SICMike Frysinger2-16/+32
The SIC latches ints from peripherals to the CEC, but the peripherals need to be able to tell the SIC when to stop. So use the incoming level to figure out when to set the int bits and when to clear it. Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2011-04-11sim: bfin: add missing GPIO pin 15Mike Frysinger2-0/+5
Each GPIO block has 16 pins, and I only added 15 in the original port list. So add the missing 16th. Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2011-04-02sim: dv-glue: fix up style a bitMike Frysinger2-7/+38
This touches up the code a bit to match GNU style. No functional changes. Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2011-04-02sim: fix up style a bitMike Frysinger14-80/+137
This touches up the code a bit to match GNU style. No functional changes. Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2011-04-01sim: bfin: add OTP output portMike Frysinger2-0/+12
This doesn't currently generate any interrupts (as there doesn't appear to be any documentation to *when* it would even do so), but since the HRM does say an interrupt line exists between the OTP and the SIC, add one for completeness sake. This will make a follow up patch easier. Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2011-03-29sim: bfin: regen configure to include new cfi deviceMike Frysinger2-1/+5
2011-03-29sim: cfi: new flash device simulationMike Frysinger5-1/+869
This simulates a CFI flash. Its pretty configurable via the device tree. For now, only basic read/write/erase operations are supported for the Intel command set, but it's easy enough to extend support. It's certainly enough to trick Das U-Boot into using it for probing, reading, writing, and erasing. Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2011-03-29sim: bfin: fix sign extension with 16bit acc add insnsMike Frysinger2-9/+9
The current implementation attempts to handle the 16bit sign extension itself. Unfortunately, it gets it right in some cases. So rather than fix that logic, just drop it in favor of using 16bit signed casts. Now gcc will take care of getting the logic right. Signed-off-by: Robin Getz <robin.getz@analog.com> Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2011-03-27sim: bfin: handle saturation with RND12 sub insnsMike Frysinger2-1/+11
The current handling of the subtraction insn with the RND12 modifier works when saturation isn't involved. So add handling for this edge case to match the hardware. Signed-off-by: Robin Getz <robin.getz@analog.com> Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2011-03-26sim: bfin: add missing VS set with add/sub insnsMike Frysinger2-0/+7
The 16bit add/sub insns missed setting the VS bit in ASTAT whenever the V bit was also set. Signed-off-by: Robin Getz <robin.getz@analog.com> Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2011-03-25sim: bfin: add hw tracing to gpio/sic port eventsMike Frysinger3-10/+64
Makes it a lot easier to find out what's going on with interrupt lines if the ports have tracing output. Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2011-03-25sim: bfin: fix GPIO logic bugs when processing eventsMike Frysinger2-4/+16
We need the DIR bit cleared, not set, in order for the pin to be treated as an input. When looking up the data value, we need to shift the "level" value over by "my_port" rather than "bit" as the latter has already been shifted over. We also should normalize the "level" coming in from the outside worlds to the set of {0,1} since those are the only values that matter to GPIOs. We need the BOTH bit set, not cleared, in order for the pin to trigger on both edges. Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2011-03-25sim: bfin: fix clear/set/toggle GPIO handlingMike Frysinger2-0/+11
The clear/set/toggle MMRs aren't backed by "real" data; they implicitly perform bit operations on the associated data register. So when we go to process writes to them, we need to adjust the pointer accordingly so that the actual backing data is modified. Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2011-03-24sim: bfin: document SIC limitationMike Frysinger2-1/+27
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2011-03-24sim: bfin: fix inverted W1C logicMike Frysinger14-17/+34
When I originally wrote the w1c helper funcs, I used it in a few places. Then I forgot how it worked and when I later documented it, I described the 3rd arg in the exact opposite way it is actually used. This error propagated to a bunch of devices registers that were not explicitly tested (a bunch of the devices are stubs which merely exist to say "no device is connected" to make device drivers happy). So once the documentation is unscrewed, fix all of the broken call sites. Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2011-03-24sim: bfin: define more UART LSR bitsMike Frysinger2-7/+16
We'll need these bits in an upcoming patch, so map out the whole LSR MMR now. Fix up indentation style while we're here. Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2011-03-24sim: bfin: fix typo in TWI stat regMike Frysinger2-1/+5
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2011-03-24sim: bfin: update VIT_MAX behavior to match hardware when Acc.X bits are setMike Frysinger2-2/+7
The Blackfin PRM says that the top 8 bits of the accumulator must be cleared when using the VIT_MAX insn, so the sim has followed this spec. Matching the hardware behavior though when the high bits are not cleared is easy to do and doesn't break existing behavior, so go for it. Signed-off-by: Robin Getz <robin.getz@analog.com> Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2011-03-24sim: bfin: always do 16bit sign extension with the SEARCH insnMike Frysinger2-0/+10
The Blackfin PRM does not cover this case, but the hardware is clear: even if the search criteria is not met (and thus a new 16bit value is loaded up into the accumulator), the accumulator undergoes 16bit sign extension. So simply reload the low signed 16bits in that case. Signed-off-by: Robin Getz <robin.getz@analog.com> Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2011-03-24sim: bfin: update AV and AC ASTAT bits with acc negationMike Frysinger2-6/+14
The Acc=-Acc insn can overflow or carry with edge values, so make sure we update the ASTAT bits accordingly to match the hardware. Also fix a thinko where we always updated AC0 even when working with A1 regs. Signed-off-by: Robin Getz <robin.getz@analog.com> Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2011-03-24sim: bfin: fix thinko in SIC pin encodingMike Frysinger2-511/+516
When encoding the SIC/pin info into unique input port ids, I used bases of 100 when I meant to use 0x100. Rather than simply fix the decoding math in the different functions, create a few helper macros to simplify the SIC/pin encoding and decoding steps. This makes the resulting tables nice & clear. And now that pins are clear, the 533 and 537 port_event handlers may easily be merged into one. Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2011-03-24sim: bfin: allow byteop[123]p src regs to be the sameMike Frysinger2-9/+5
The hardware allows the byteop[123]p insns to use the same src reg pair, so remove the combination check in the sim. Signed-off-by: Robin Getz <robin.getz@analog.com> Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2011-03-24sim: bfin: fix thinko in bfin_gpio bus addressesMike Frysinger2-30/+38
The bus addresses have to be valid numbers, so 'g' and 'h' won't work. Oddly, the common code silently ignored this which is why I didn't notice in the first place. Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2011-03-21 * gennltvals.sh: Search sys/_default_fcntl.h, in addition toKevin Buettner5-384/+390
fcntl.h and sys/fcntl.h, for constants. * nltvals.def: Regenerate. * sim-io.c (sim_io_stat, sim_io_fstat): New functions. * sim-io.h (sys/types.h, sys/stat.h): Include. (sim_io_stat, sim_io_fstat): Declare.
2011-03-21 * simops (OP_10007E0): Update errno handling as most trapsKevin Buettner2-3/+88
do not invoke the host's functionality directly. Invoke sim_io_stat() instead of stat() for implementing TARGET_SYS_stat. Implement TARGET_SYS_fstat, TARGET_SYS_rename, and TARGET_SYS_unlink.
2011-03-17sim: bfin: check for kill/preadMike Frysinger5-2/+25
If the host system (like Windows) doesn't support these functions, then make sure we don't use them. Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2011-03-15sim: bfin: add GPIO device simulationMike Frysinger7-28/+369
This takes care of the MMR interface and pushing up interrupts. Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2011-03-15sim: bfin: fix brace styleMike Frysinger27-27/+54
2011-03-15sim: bfin: fix brace styleMike Frysinger58-161/+342
2011-03-15sim: bfin: handle AZ updates with 16bit adds/subsMike Frysinger2-1/+6
We weren't updating AZ when doing a 16bit add or sub insn. Implement it. Signed-off-by: Robin Getz <robin.getz@analog.com> Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2011-03-15sim: bfin: skip acc/ASTAT updates for movesMike Frysinger2-6/+10
No point in moving unchanged acc values to the acc regs, and avoid updating the acc ASTAT bits when only reading. This fixes incorrect changing of the ASTAT bits when they're only being read. Signed-off-by: Robin Getz <robin.getz@analog.com> Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2011-03-15sim: bfin: handle AN (negative overflows) in dsp mult insnsMike Frysinger2-8/+40
The current dsp mult handler does not take care of overflows which turn values negative (and thus set AN in ASTAT). So implement it. Signed-off-by: Robin Getz <robin.getz@analog.com> Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2011-03-15sim: bfin: handle V overflows in dsp mult insnsMike Frysinger2-7/+15
The current dsp mult handler does not take care of overflows and updating the V ASTAT bit. So implement it. Signed-off-by: Robin Getz <robin.getz@analog.com> Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2011-03-15sim: bfin: decode ASTAT on failureMike Frysinger2-34/+79
When testing ASTAT regs, specific bit differences carry a lot more meaning than when checking the value of a data register. So automatically decode the bits of the two values and print things out so that people don't have to manually do it themselves every time. Signed-off-by: Robin Getz <robin.getz@analog.com> Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2011-03-15sim: bfin: handle saturation with fract multiplicationsMike Frysinger2-0/+6
The saturation behavior with fract modes differs from non-fract modes. Signed-off-by: Robin Getz <robin.getz@analog.com> Signed-off-by: Mike Frysinger <vapier@gentoo.org>
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