Age | Commit message (Collapse) | Author | Files | Lines |
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* reset.c (frv_initialize): Call frv_register_control_init first.
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* profile.h (update_FR_ptime): New prototype.
(update_FRdouble_ptime): Ditto.
(update_SPR_ptime): Ditto.
(increase_ACC_busy): Ditto.
(enforce_full_acc_latency): Ditto.
(post_wait_for_SPR): Ditto.
* profile.c (update_FR_ptime): Moved here from profile-fr500.c.
(update_FRdouble_ptime): Ditto.
(update_SPR_ptime): New function.
(increase_ACC_busy): Ditto.
(enforce_full_acc_latency): Ditto.
(vliw_wait_for_fdiv_resource): Correct resource name.
(vliw_wait_for_fsqrt_resource): Ditto.
(post_wait_for_SPR): New function.
* profile-fr500.c (frvbf_model_fr500_u_commit): New function.
(frvbf_model_fr500_u_gr2fr): Pass out_FRk as output register to
adjust_float_register_busy.
(frvbf_model_fr500_u_gr_load): Record latency of SPR registers.
(frvbf_model_fr500_u_fr_load): Wait for and record latency of SPR
registers.
(frvbf_model_fr500_u_float_arith): Ditto.
(frvbf_model_fr500_u_float_dual_arith): Ditto.
(frvbf_model_fr500_u_float_div): Ditto.
(frvbf_model_fr500_u_float_sqrt): Ditto.
(frvbf_model_fr500_u_float_convert): Ditto.
(update_FR_ptime): Moved to profile.c
(update_FRdouble_ptime): Moved to profile.c
* profile-fr400.c (update_FR_ptime): Removed. Identical to functions
for other machines.
(update_FRdouble_ptime): Ditto.
* arch.h,cpu.h,sem.c,decode.[ch],model.c,sem.c: Regenerated.
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* sim/frv/nldqi.cgs: Remove. This insn was never implemented
by Fujitsu.
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* sim/frv/rstqf.cgs: Use nldq instead of nldqi.
* sim/frv/rstq.cgs: Use nldq instead of nldqi.
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* registers.c (frv_check_spr_read_access): Check for access to
ACC4-ACC63 and ACCG4-ACCG63.
* profile.h (frv-desc.h): #include it.
(spr_busy): New member of FRV_PROFILE_STATE.
(spr_latency): Ditto.
(GNER_FOR_GR): New macro.
(FNER_FOR_FR): New maccro.
(update_SPR_latency): New function.
(vliw_wait_for_SPR): New function.
* profile.c (profile-fr550.h): #include it.
(update_latencies): Update SPR latencies.
(update_target_latencies): Ditto.
(update_SPR_latency): New function.
(vliw_wait_for_SPR): New function.
* profile-fr500.c (frvbf_model_fr500_u_idiv): Record GNER latency.
(frvbf_model_fr500_u_trap): Removed unused variable, ps.
(frvbf_model_fr500_u_check): Ditto.
(frvbf_model_fr500_u_clrgr): New unit modeller for fr500.
(frvbf_model_fr500_u_clrfr): Ditto.
(frvbf_model_fr500_u_spr2gr): Wait for SPR.
(frvbf_model_fr500_u_gr2spr): Ditto.
* frv-sim.h (H_SPR_ACC4): New macro.
(H_SPR_ACCG4): New macro;
(H_SPR_ACC0): Removed.
(H_SPR_ACCG0): Removed.
* arch.h,model.c,sem[ch],decode.[ch]: Regenerated.
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* sim/testsuite/sim/frv/movgs.cgs: Change lcr to spr[273],
which according to the comments seems to be the intent.
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* profile.c (slot_names): FM1 was listed twice. Changed first
instance to FM0. Added IALL, FMALL and FMLOW.
(print_parallel): Don't examine slots with no insns.
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* sim/frv/maddaccs.cgs: move to fr400 subdirectory.
* sim/frv/msubaccs.cgs: move to fr400 subdirectory.
* sim/frv/masaccs.cgs: move to fr400 subdirectory.
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* frv.c (do_media_average): Select machine using a switch.
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On behalf of Doug Evans <dje@sebabeach.org>
* Makefile.in (stamp-arch,stamp-cpu,stamp-xcpu): Pass archfile to cgen.
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On behalf of Doug Evans <dje@sebabeach.org>
* Makefile.in (stamp-arch,stamp-cpu, stamp-desc): Pass archfile to cgen.
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On behalf of Doug Evans <dje@sebabeach.org>
* Makefile.in (stamp-arch,stamp-cpu): Pass archfile to cgen.
Remove copying of .cpu file to cgen/cpu, no longer needed.
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On behalf of Doug Evans <dje@sebabeach.org>
* cgen.sh: New arg archfile.
* Make-common.in (cgen-arch,cgen-cpu,cgen-defs,cgen-decode,
cgen-cpu-decode,cgen-desc): Update call to cgen.sh.
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* cpu.h, model.c, sem.c, decode.h, decode.c: Regenerated.
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* sim/frv/fr500/mclracc.cgs: Change mach to 'all',
to be consistant with other tests in the directory.
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* sim/frv/interrupts/Ipipe-fr400.cgs: New file.
* sim/frv/interrupts/Ipipe-fr500.cgs: New file.
* sim/frv/interrupts/Ipipe.cgs: Remove (replaced by above).
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* Makefile.in (stamp-arch): Copy frv.cpu from $(srcdir)../../cpu
temporarily when regenerating files.
(stamp-cpu): Ditto.
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* MAINTAINERS: Add myself as maintainer of the FRV port.
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Dave Brolley <brolley@redhat.com>
* frv/: New directory, simulator for the Fujitsu FR-V.
* testsuite/frv-elf/: New directory.
* testsuite/sim/frv/: New directory.
* configure.in: Add frv configury.
* configure: Regenerate.
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Dave Brolley <brolley@redhat.com>
* cgen-par.h (flags, word1): New target-specific
fields of CGEN_WRITE_QUEUE_ELEMENT.
(CGEN_WRITE_QUEUE_ELEMENT_FLAGS): New accessor macro.
(CGEN_WRITE_QUEUE_ELEMENT_WORD1): New accessor macro.
* gennltvals.sh: Add frv target.
* nltvals.def: Add frv target.
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On behalf of Dave Brolley
* sim/frv: New testsuite.
* frv-elf: New testsuite.
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2003-08-28 Andrew Cagney <cagney@redhat.com>
* dv-glue.c (hw_glue_finish): Change %d to %ld to match sizeof.
* sim-options.c (print_help): Cast the format with specifier to
"int".
Index: mn10300/ChangeLog
2003-08-28 Andrew Cagney <cagney@redhat.com>
* dv-mn103ser.c (do_polling_event): Change type of "serial_reg" to
"long".
(read_status_reg): Cast "serial_reg" to "long".
* dv-mn103tim.c (do_counter_event): Change type of "timer_nr" to
"long".
(do_counter6_event, write_mode_reg, write_tm6md): Ditto.
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* macl.s: New file.
* macw.s: New file.
* allinsn.exp: Add new tests for mac.w and mac.l.
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* sim/sh/gencode.c ( tab[] ): Addition of MAC.L handler and
correction for MAC.W handler
* sim/sh/interp.c ( macl ): New Function. Implementation of
MAC.L handler.
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* MAINTAINERS: Andrew Cagney (mips) and Geoff Keating (ppc) drop
maintenance. List igen and sh maintainers. Mention that target
and global maintainers pick up the slack.
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control the translation.
(m68hc11tim_print_timer): Update cycle_to_string conversion.
(m68hc11tim_timer_event): Fix handling of output
compare register with its interrupts.
(m68hc11tim_io_write_buffer): Check output compare
after setting M6811_TMSK1.
(m68hc11tim_io_read_buffer): Fix compilation warning.
* dv-m68hc11.c (m68hc11_option_handler): Likewise.
* dv-m68hc11spi.c (m68hc11spi_info): Likewise.
* dv-m68hc11sio.c (m68hc11sio_info): Likewise.
* interrupts.c (interrupts_info): Likewise.
(interrupts_reset): Recognize bootstrap mode.
* sim-main.h (PRINT_CYCLE, PRINT_TIME): New defines.
(_sim_cpu): Add cpu_start_mode.
(cycle_to_string): Add flags member.
* m68hc11_sim.c (OPTION_CPU_BOOTSTRAP): New option.
(cpu_options): Declare new option bootstrap.
(cpu_option_handler): Handle it.
(cpu_info): Update call to cycle_to_string.
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the physical address in virtual address.
(struct _sim_cpu): Add memory bank members.
* m68hc11_sim.c (cpu_initialize): Clear memory bank parameters.
* interp.c (sim_hw_configure): Create memory bank according to memory
bank parameters.
(sim_get_bank_parameters): New function to obtain memory bank config
from the symbol table.
(sim_prepare_for_program): Call it to obtain the memory bank parameters.
(sim_open): Call sim_prepare_for_program.
* dv-m68hc11.c (m68hc11cpu_io_write_buffer): Use memory bank parameters
to check if address is within bank window.
(m68hc11cpu_io_read_buffer): Likewise.
(attach_m68hc11_regs): Map the memory bank according to memory bank
parameters.
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* sim-main.h (print_io_word): Declare.
* dv-m68hc11tim.c (tmsk1_desc): New description table for TMSK1.
(tflg1_desc): Likewise for TFLG1.
(m68hc11tim_info): Print input and output compare registers
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* gencode.c (expand_ppi_code): Comment spelling fix.
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* cmpw.s: Add test for less-than-zero immediate.
* shll.s: Test for shll reg, reg.
* shlr.s: Test for shlr reg, reg.
* mova.s: Add dozens of new mova tests.
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* compile.c (decode): Enhancements for mova.
Initialize cst, reg, and rdisp inside the loop, for each
new instruction. Defer correction of the disp2 values until
later, and then adjust them by the size of the first operand,
rather than the size of the instruction.
(sim_resume): For mova, adjust the size of the second operand
according to the type of the first operand (INDEXB vs. INDEXW).
In cases where there is only one operand, the other two must
both be composed on the fly.
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* pshai.s, pshar.s, pshli.s, pshlr.s: New files.
* allinsn.exp: Add psha, pshl tests.
* pdec.s, pinc.s, padd.s, paddc.s: New files.
* allinsn.exp: Add pdec, pinc, padd, paddc tests.
* pand.s, pdmsb.s: New files.
* allinsn.exp: Add pand, pdmsb tests.
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* allinsn.exp, testutils.inc, add.s, fabs.s, fadd.s, fcmpeq.s,
fcmpgt.s, fcnvds.s, fcnvsd.s, fdiv.s, fldi0.s, fldi1.s, flds.s,
float.s, fmac.s, fmov.s, fmul.s, fneg.s, frchg.s, fschg.s,
fsqrt.s, fsub.s, ftrc.s, shll16.s, shll2.s, shll8.s, shll.s,
shlr16.s, shlr2.s, shlr8.s, shlr.s, swap.s: New files.
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* gencode.c (pshl): Change < to <= (shift by 16 is allowed).
Cast argument of >> to unsigned to prevent sign extension.
(psha): Change < to <= (shift by 32 is allowed).
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* gencode.c: Fix typo in comment.
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* gencode.c: A few more fix-ups of refs and defs.
(frchg): Raise SIGILL if in double-precision mode.
(ldtlb): We don't simulate cache, so this is a no-op.
(movsxy_tab): Correct a few bit pattern errors.
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* gencode.c (prnd): Clear LSW of result to zeros.
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* pmuls.s: New file.
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* gencode.c (pmuls): Expression is mis-parenthesized.
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* configure.in: Add testsuite to extra_subdirs for sh.
* configure: Regenerate.
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* sim/sh: New directory. Tests for Renesas sh family.
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* allinsn.exp, testutils.inc, add.s, fabs.s, fadd.s, fcmpeq.s,
fcmpgt.s, fcnvds.s, fcnvsd.s, fdiv.s, fldi0.s, fldi1.s, flds.s,
float.s, fmac.s, fmov.s, fmul.s, fneg.s, frchg.s, fschg.s,
fsqrt.s, fsub.s, ftrc.s, shll16.s, shll2.s, shll8.s, shll.s,
shlr16.s, shlr2.s, shlr8.s, shlr.s, swap.s: New files.
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