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AgeCommit message (Expand)AuthorFilesLines
2022-12-22sim: mips: trim redundant igen settingsMike Frysinger2-18/+0
2022-12-22sim: mips: merge mips64* with existing multi-run buildMike Frysinger2-10/+4
2022-12-22sim: mips: merge mips64vr5000 with existing multi-run buildMike Frysinger2-8/+2
2022-12-22sim: mips: switch from SIM_ADDR to address_wordMike Frysinger2-31/+13
2022-12-22sim: v850: switch from SIM_ADDR to address_wordMike Frysinger2-4/+4
2022-12-22sim: switch sim_{read,write} APIs to 64-bit all the time [PR sim/7504]Mike Frysinger13-58/+60
2022-12-22sim: use bfd_vma when reading start addr from bfd infoMike Frysinger11-12/+12
2022-12-22sim: m32r: include sim-hw.h for sim_hw_parseMike Frysinger1-0/+1
2022-12-22sim: mips: merge mips64vr4300 with existing multi-run buildMike Frysinger2-8/+2
2022-12-21sim: mips: match target on cpu settingsMike Frysinger2-26/+26
2022-12-21sim: mips: move fpu bitsize defines to top-level configureMike Frysinger8-71/+44
2022-12-21sim: mips: move bitsize defines to top-level configureMike Frysinger8-99/+48
2022-12-21sim: mips: move subtarget defines to top-level configureMike Frysinger8-43/+68
2022-12-21sim: mips: always resolve active bfd mach dynamicallyMike Frysinger3-106/+3
2022-12-21sim: hw-config.h: move generation to top-levelMike Frysinger3-30/+54
2022-12-21sim: build: hoist lists of hw devices upMike Frysinger16-127/+190
2022-12-21sim: build: hoist lists of common objects upMike Frysinger4-131/+167
2022-12-21sim: fully merge sim_cpu_base into sim_cpuMike Frysinger1-26/+19
2022-12-21sim: enable common sim_cpu usage everywhereMike Frysinger29-66/+1
2022-12-21sim: or1k: invert sim_cpu storageMike Frysinger5-30/+43
2022-12-21sim: m32r: invert sim_cpu storageMike Frysinger5-14/+10
2022-12-21sim: lm32: invert sim_cpu storageMike Frysinger3-12/+7
2022-12-21sim: iq2000: invert sim_cpu storageMike Frysinger3-11/+7
2022-12-21sim: frv: invert sim_cpu storageMike Frysinger3-23/+18
2022-12-21sim: cris: invert sim_cpu storageMike Frysinger6-239/+244
2022-12-21sim: bpf: invert sim_cpu storageMike Frysinger3-7/+13
2022-12-21sim: cgen: prep for inverting sim_cpu storageMike Frysinger2-0/+15
2022-12-21sim: riscv: invert sim_cpu storageMike Frysinger3-191/+258
2022-12-21sim: pru: invert sim_cpu storageMike Frysinger3-8/+31
2022-12-21sim: example-synacor: invert sim_cpu storageMike Frysinger3-37/+47
2022-12-21sim: h8300: invert sim_cpu storageMike Frysinger2-34/+36
2022-12-21sim: m68hc11: invert sim_cpu storageMike Frysinger10-354/+446
2022-12-21sim: mips: invert sim_cpu storageMike Frysinger2-73/+90
2022-12-21sim: v850: invert sim_cpu storageMike Frysinger3-20/+23
2022-12-21sim: mcore: invert sim_cpu storageMike Frysinger2-27/+41
2022-12-21sim: aarch64: invert sim_cpu storageMike Frysinger5-108/+152
2022-12-21sim: microblaze: invert sim_cpu storageMike Frysinger3-8/+8
2022-12-21sim: avr: invert sim_cpu storageMike Frysinger2-99/+108
2022-12-21sim: moxie: invert sim_cpu storageMike Frysinger2-14/+13
2022-12-21sim: msp430: invert sim_cpu storageMike Frysinger3-120/+106
2022-12-21sim: ft32: invert sim_cpu storageMike Frysinger3-95/+99
2022-12-21sim: bfin: invert sim_cpu storageMike Frysinger2-10/+5
2022-12-20sim: sim_cpu: invert sim_cpu storageMike Frysinger7-39/+45
2022-12-20sim: move register headers into sim/ namespace [PR sim/29869]Mike Frysinger16-16/+16
2022-12-20sim: ppc: drop old dgen.c generatorMike Frysinger3-363/+6
2022-12-20sim: ppc: move spreg.[ch] files to the source treeMike Frysinger5-0/+1608
2022-12-19sim: ppc: change spreg switch table generation to compile-timeMike Frysinger4-15/+16
2022-12-19sim: dv-core: add hw_detach_address method [PR sim/25211]Mike Frysinger2-13/+18
2022-11-12sim: pru: Fix behaviour when loop count is zeroDimitar Dimitrov2-2/+43
2022-11-11sim: igen: cleanup archaic pointer-to-long printf castsMike Frysinger4-53/+49
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