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AgeCommit message (Expand)AuthorFilesLines
1997-11-10Test rachi instruction.Andrew Cagney3-3/+44
1997-11-10* callback.c (os_poll_quit): Replace _WIN32 with _MSC_VER.Andrew Cagney1-0/+4
1997-11-06Replace global IPC with function argument cia or current instructionAndrew Cagney5-60/+78
1997-11-06Fix computation of sim_events_time when sim_events_slip is loosing it.Andrew Cagney2-34/+31
1997-11-06IGEN likes to cache the current instruction address (CIA). Change theAndrew Cagney5-112/+172
1997-11-06Allow separate single character and long options.Andrew Cagney1-0/+17
1997-11-05Add option --enable-sim-igen to mips configuration. Allows user toAndrew Cagney2-17/+50
1997-11-05Rewrite the MIPS simulator's memory model so that it uses the genericAndrew Cagney8-641/+437
1997-11-05Delete -l and -n options, didn't do anything.Andrew Cagney3-51/+28
1997-11-05Rewrite sim_monitor (implements read, write, open, et.al. systemAndrew Cagney3-323/+249
1997-11-04* sim-endian.h (U16_8): ImplementAndrew Cagney1-0/+13
1997-11-04 * gen-idecode.c (print_jump_until_stop_body): Use `#if 0' instead ofBrendan Kehoe1-0/+5
1997-11-04do not assume NULL is an integer constantMichael Meissner1-0/+5
1997-11-04Correct r5900 sanitization.Gavin Romig-Koch2-1/+3
1997-10-31Make memory regions layered (just like existing device regions) soAndrew Cagney4-123/+223
1997-10-30Patches to support generating an executing environment.Nick Clifton1-4/+59
1997-10-30 * sim-core.h (sim_core_write_8): Define.Doug Evans2-0/+5
1997-10-29 * gencode.c: Add tx49 configury and insns.Gavin Romig-Koch5-15/+97
1997-10-29common/sim-bits.h: Document ROTn macro.Andrew Cagney8-22/+726
1997-10-28Add support for 16 byte quantities to sim-endian macro H2T.Andrew Cagney10-75/+153
1997-10-28Implement sim_core_{read,write}_word using sim_core_{read,write}_<N>.Andrew Cagney4-13/+27
1997-10-27 * sem-ops.h (U{DIV,MOD}[BHSD]I): Use unsigned division.Doug Evans2-12/+24
1997-10-27 * sim-endian.h: Disable 16 byte support.Doug Evans2-7/+9
1997-10-27 * sim-n-endian.h: Add TAGS entrys for 16 byte versions.Doug Evans1-0/+4
1997-10-27Fix typo.Doug Evans1-1/+1
1997-10-27Separate r5900 specifoc and mips16 instructions.Andrew Cagney9-5179/+2770
1997-10-27Add mips64vr5400 to configuration listAndrew Cagney6-38/+636
1997-10-27Add include-file support to igen.Andrew Cagney5-417/+1348
1997-10-27Add 128 bit transfers to sim core.Andrew Cagney7-66/+180
1997-10-25 * sim/mips/gencode.c (build_instruction): Follow sim_write's lead in usingGavin Romig-Koch2-1/+7
1997-10-25Correct name of file given in ChangeLog for change: Pass lma_p andAndrew Cagney3-3/+3
1997-10-24Add basic igen configuration to autoconf. Disable.Andrew Cagney4-18/+244
1997-10-24Add function to fetch 32bit instructionsAndrew Cagney4-119/+154
1997-10-24Checkpoint IGEN version of mips simAndrew Cagney1-152/+157
1997-10-24Add function sim_events_slip()Andrew Cagney2-16/+56
1997-10-24Address MSC compiler issues in d10v_sim.hAndrew Cagney1-0/+8
1997-10-22Add LMA_P and DO_WRITE arguments to sim/common/sim-load.c:sim_load_file().Andrew Cagney9-9/+102
1997-10-22* nrun.c (main): Exit if bfd_openr fails.Doug Evans1-0/+1
1997-10-22 * nrun.c (main): Remove useless test of name != NULL.Doug Evans2-3/+20
1997-10-21 * simops.c: Correctly handle register restores for "ret" and "retf"Jeff Law2-66/+71
1997-10-21Use SIM*_OVERFLOW_RESULT defined in sim-alu.hAndrew Cagney2-2/+7
1997-10-21Pacify GCC -WallAndrew Cagney1-0/+6
1997-10-21Output pc profile statistics once gathered.Andrew Cagney2-9/+5
1997-10-21Delete profile support from MIPS simulator, use sim/common/sim-profileAndrew Cagney5-225/+46
1997-10-20Have single bit macros return an unsigned result. Avoids risk (andAndrew Cagney2-16/+33
1997-10-20Make mips registers of type unsigned_word.Andrew Cagney3-3/+14
1997-10-20Add 8 bit arithmetic to sim-alu.Andrew Cagney3-2/+15
1997-10-17Preliminary tests for sim-alu module.Andrew Cagney3-0/+189
1997-10-16Move register definitions and macros out of interp.c and into sim-main.hAndrew Cagney4-274/+362
1997-10-16Checkpoint IGEN version of MIPS simulator.Andrew Cagney1-248/+218
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