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AgeCommit message (Expand)AuthorFilesLines
2021-11-16sim: run: support concise env var settingsMike Frysinger2-2/+23
2021-11-16sim: nrun: add --env-{set,unset,clear} command line optionsMike Frysinger5-10/+107
2021-11-16sim: syscall: hoist argc/argn/argnlen to common codeMike Frysinger2-33/+40
2021-11-16sim: syscall: fix argvlen & argv implementationMike Frysinger1-42/+50
2021-11-16sim: callback: expose argv & environMike Frysinger13-10/+73
2021-11-16sim: keep track of program environment stringsMike Frysinger14-7/+85
2021-11-16sim: iq2000: fix some missing prototypes warningsMike Frysinger4-5/+10
2021-11-15sim: cris: make error message test a little more flexibleMike Frysinger1-1/+1
2021-11-15sim: run: fix crash in argc==0 error situationMike Frysinger1-7/+17
2021-11-15sim: cris: touch up rvdummy handlingMike Frysinger1-2/+2
2021-11-15sim: cris: replace custom "dest" test field with new --argv0Mike Frysinger4-8/+5
2021-11-15sim: run: add --argv0 option to control argv[0]Mike Frysinger4-4/+27
2021-11-15sim: split program path out of argv vectorMike Frysinger31-119/+40
2021-11-15sim: bfin: fix mach/xfail usage in testsMike Frysinger4-6/+6
2021-11-13sim: sh: fix switch-bool warningsMike Frysinger1-51/+28
2021-11-13sim: sh: rework carry checks to not rely on integer overflowsMike Frysinger1-4/+4
2021-11-11sim: testsuite: drop sim_compile cover functionMike Frysinger2-14/+1
2021-11-11sim: cris: stop testing a.out explicitly [ld/13900]Mike Frysinger1-14/+0
2021-11-11sim: io: tweak compiler workaround with error outputMike Frysinger1-3/+3
2021-11-10sim: testsuite: delete unused arm remote host logicMike Frysinger3-24/+0
2021-11-10sim: synacor: simplify test generationMike Frysinger2-7/+4
2021-11-10sim: frv: flip trapdump default back to offMike Frysinger2-2/+2
2021-11-09sim: sh: simplify testsuite a bitMike Frysinger8-82/+12
2021-11-08sim: cris: clean up missing func prototype warningsMike Frysinger4-6/+6
2021-11-06sim: sh: fix conversion of PC to an integerMike Frysinger1-1/+1
2021-11-06sim: sh: clean up time(NULL) callMike Frysinger1-1/+1
2021-11-06sim: sh: break utime logic out of _WIN32 checkMike Frysinger1-1/+8
2021-11-06sim: sh: drop errno externMike Frysinger1-1/+0
2021-11-06sim: sh: fix isnan redefinition with mingw targetsMike Frysinger1-0/+2
2021-11-06sim: arm/bfin/rx: undefine page size from system headersMike Frysinger3-0/+5
2021-11-06sim: ppc: switch to libiberty environ.hMike Frysinger1-2/+2
2021-11-06sim: sh: enable -Werror everywhereMike Frysinger1-3/+0
2021-11-06sim: sh: fix uninitialized variable usage with pdmsbMike Frysinger1-1/+1
2021-11-06sim: sh: constify a few read-only lookup tablesMike Frysinger1-6/+6
2021-11-06sim: sh: fix various parentheses warningsMike Frysinger2-11/+11
2021-11-06sim: sh: fix unused-value warningsMike Frysinger1-3/+3
2021-11-06sim: sh: rework register layout with anonymous unions & structsMike Frysinger3-90/+82
2021-11-06sim: mips: use sim_fpu_to{32,64}u to fix build warningsTiezhu Yang2-7/+4
2021-11-06sim: clarify license text via COPYING fileMike Frysinger3-1155/+0
2021-11-03sim: mips: fix missing prototype in multi-run generationMike Frysinger2-0/+4
2021-11-03sim: ppc: inline common sim-fpu.c logicMike Frysinger3-33/+2
2021-11-03sim: ppc: switch to common builds for callback objectsMike Frysinger3-37/+6
2021-11-03sim: mloop: mark a few conditionally used funcs as unusedMike Frysinger2-3/+4
2021-11-02sim: hoist cgen mloop rules up to common buildsMike Frysinger17-199/+707
2021-11-02sim: hoist mn10300 & v850 igen rules up to common buildsMike Frysinger7-153/+386
2021-11-02sim: hoist gencode & opc2c build rules up to common buildsMike Frysinger12-119/+625
2021-11-02gdb/sim: update my email addressAndrew Burgess1-1/+1
2021-11-01sim: iq2000: reduce -Wno-error scopeMike Frysinger2-5/+5
2021-11-01sim: lm32: reduce -Wno-error scopeMike Frysinger3-5/+5
2021-11-01sim: frv: reduce -Wno-error scopeMike Frysinger1-2/+2
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