riscv-gnu-toolchain/gdb.git - Unnamed repository; edit this file 'description' to name the repository.

Age	Commit message (Collapse)	Author	Files	Lines
1999-04-16	Initial creation of sourceware repositorygdb-4_18-branchpoint	Stan Shebs	1	-0/+8

1999-04-16	Initial creation of sourceware repository	Stan Shebs	1	-8/+0

1997-09-03	Add real SIM_DESC arg to v850 simulator.	Andrew Cagney	1	-163/+1
	Add --enable-sim-warnings, use/fix errors. Add --enable-sim-endian, don't use. Add common modules. Don't yet use most.
1997-09-01	Compile from UNIX to cygwin32.	Andrew Cagney	1	-23/+50

1996-10-24	* Makefile.in: Get rid of srcroot. Set all INSTALL macros via	Stu Grossman	1	-18/+60
	autoconf. * gencode.c (write_opcodes): Pad operands field to account for MSVC braindamage. * simops.c: Include errno.h. Exclude SYS_chown, since MSVC doesn't support it. (Why is this here in the first place?!?) * v850_sim.h: Get rid of 64 bit defs. Also, get rid of #elif's. Change number of operands in struct simops from 9 to 6. Define SIGTRAP and SIGQUIT for MSVC.
1996-09-03	* interp.c: OP should be an array of 32bit operands!	Jeff Law	1	-24/+15
	(v850_callback): Declare. (do_format_5): Fix extraction of OP[0]. (sim_size): Remove debugging printf. (sim_set_callbacks): Do something useful. (sim_stop_reason): Gross hacks to get c-torture running. * simops.c: Simplify code for computing targets of bCC insns. Invert 's' bit if 'ov' bit is set for some instructions. Fix 'cy' bit handling for numerous instructions. Make the simulator stop when a halt instruction is encountered. Very crude support for emulated syscalls (trap 0). * v850_sim.h: Include "callback.h" and declare v850_callback. Items in the operand array are 32bits. Fixes & syscall stuff.
1996-08-30	* v850_sim.h (struct _state): Remove "psw" field. Add	Jeff Law	1	-2/+1
	"sregs" field. (PSW): Remove bogus definition. * simops.c: Change condition code handling to use the psw register within the sregs array. Handle "ldsr" and "stsr".
1996-08-29	* interp.c (hash): Update to be more accurate.	Jeff Law	1	-35/+35
	(lookup_hash): Call hash rather than computing the hash code here. (do_format_1_2): Handle format 1 and format 2 instructions. Get operands correctly and call the target function. (do_format_6): Get operands correctly and call the target function. (do_formats_9_10): Rough cut so shift ops will work. (sim_resume): Tweak to deal with format 1 and format 2 handling in a single funtion. Don't update the PC for format 3 insns. Fix typos. * simops.c: Slightly reorganize. Add condition code handling to "add", "addi", "and", "andi", "or", "ori", "xor", "xori" and "not" instructions. * v850_sim.h (reg_t): Registers are 32bits. (_state): The V850 has 32 general registers. Add a 32bit psw and pc register too. Add accessor macros Fixing lots of stuff. Starting to add condition code support. Basically check pointing the work to date.
1996-08-29	* ChangeLog, Makefile.in, configure, configure.in, v850_sim.h,	Jeff Law	1	-0/+111
	gencode.c, interp.c, simops.c: Created. So we've got something to hack on.