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2008-02-06* simops.c (OP_1C007E0): Compensate for 64 bit hosts.DJ Delorie1-2/+2
(OP_18007E0): Likewise. (OP_2C007E0): Likewise. (OP_28007E0): Likewise. * v850.igen (divh): Likewise.
2008-02-06Index: ChangeLogDJ Delorie1-18/+18
* configure.ac (v850): V850 now has a testsuite. * configure (v850): Likewise. Index: testsuite/ChangeLog * sim/v850/: New directory. * sim/v850/allinsns.exp: New. * sim/v850/bsh.cgs: New. * sim/v850/div.cgs: New. * sim/v850/divh.cgs: New. * sim/v850/divh_3.cgs: New. * sim/v850/divhu.cgs: New. * sim/v850/divu.cgs: New. * sim/v850/sar.cgs: New. * sim/v850/satadd.cgs: New. * sim/v850/satsub.cgs: New. * sim/v850/satsubi.cgs: New. * sim/v850/satsubr.cgs: New. * sim/v850/shl.cgs: New. * sim/v850/shr.cgs: New. * sim/v850/testutils.cgs: New. * sim/v850/testutils.inc: New. Index: v850/ChangeLog * simops.c (OP_C0): Correct saturation logic. (OP_220): Likewise. (OP_A0): Likewise. (OP_660): Likewise. (OP_80): Likewise. * simops.c (OP_2A0): If the shift count is zero, clear the carry. (OP_A007E0): Likewise. (OP_2C0): Likewise. (OP_C007E0): Likewise. (OP_280): Likewise. (OP_8007E0): Likewise. * simops.c (OP_2C207E0): Correct PSW flags for special divu conditions. (OP_2C007E0): Likewise, for div. (OP_28207E0): Likewise, for divhu. (OP_28007E0): Likewise, for divh. Also, sign-extend the correct operand. * v850.igen (divh): Likewise, for 2-op divh. * v850.igen (bsh): Fix carry logic.
2003-09-05Add support for v850e1 instructionsNick Clifton1-0/+62
2003-04-06* simops.c (OP_40): Delete. Move code to...Nick Clifton1-1/+42
* v850-igen.c (): ...Here. Sign extend the first operand. * simops.h (OP_40): Remove prototype.
2002-09-19Remove v850ea referencesNick Clifton1-316/+0
2000-05-30Remove illegal instruciton pattern, since it is the same as the breakpointNick Clifton1-7/+0
pattern.
2000-05-08* merge from internal treeFrank Ch. Eigler1-4/+15
2000-04-14 Gary Thomas <gthomas@redhat.com> * v850.igen: Define 'br *' as illegal since this is the only way to provide a breakpoint on some v850 family processors.
2000-03-25* more compatibility with v850 hardwareFrank Ch. Eigler1-0/+7
2000-03-24 Frank Ch. Eigler <fche@redhat.com> * v850.igen (ilgop): New insn pattern for four-byte breakpoints.
1999-04-16Initial creation of sourceware repositorygdb-4_18-branchpointStan Shebs1-0/+1407
1999-04-16Initial creation of sourceware repositoryStan Shebs1-1461/+0
1997-12-05Reverrt BREAK value back to its old valueNick Clifton1-1/+1
1997-12-04Fixed sanitization,Nick Clifton1-208/+64
Changed pattern for break insn.
1997-09-19Clean up tracing for Bcond & jmp insns.Andrew Cagney1-128/+100
Fix computation of disp16 and disp22. Clean up tracing of sld* insns.
1997-09-19Fix cmov immed.Andrew Cagney1-12/+56
1997-09-19Fix cmov insn.Andrew Cagney1-1/+3
1997-09-17Clean up more tracing.Andrew Cagney1-3/+21
FIX interrupt delivery - was zapping PSW before it had been saved. FIX interrupt return, was one instruction out.
1997-09-17Fix tracing for: "ctret", "bsw", "hsw"Andrew Cagney1-36/+72
Fix bugs in: "bsh", "callt", "stsr".
1997-09-16Smooth some of ALU tracing's rough edges.Andrew Cagney1-39/+69
Fix switch insn.
1997-09-16Restrict ldsr (load system register) to modifying just non-reserved PSW bits.Andrew Cagney1-2/+16
For v850eq, include PSW[US] in bits that can be modified.
1997-09-16Add v850e version of breakpoint instruction.Andrew Cagney1-5/+16
1997-09-15For instructions moved into v850.igen was computing (wrong) NIA whenAndrew Cagney1-10/+10
this wasn't needed.
1997-09-15Fix sanitization for v850 V v850e V v850eqAndrew Cagney1-11/+267
1997-09-15For v850eq start up with US bit set.Andrew Cagney1-2/+26
Let sim_analyze_program determine the architecture. Fix various sanitizations.
1997-09-12Check reserved bits before executing instructions.Andrew Cagney1-1/+48
Make v850[eq] the the default simulator. Report illegal instructions. Include v850e instructions in v850eq.
1997-09-08Add multi-sim support to v850/v850e/v850eq simulators.Andrew Cagney1-0/+1151
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