riscv-gnu-toolchain/gdb.git - Unnamed repository; edit this file 'description' to name the repository.

Age	Commit message (Expand)	Author	Files	Lines
2000-05-30	Remove illegal instruciton pattern, since it is the same as the breakpoint	Nick Clifton	1	-7/+0
2000-05-08	* merge from internal tree	Frank Ch. Eigler	1	-4/+15
2000-03-25	* more compatibility with v850 hardware	Frank Ch. Eigler	1	-0/+7
1999-04-16	Initial creation of sourceware repositorygdb-4_18-branchpoint	Stan Shebs	1	-0/+1407
1999-04-16	Initial creation of sourceware repository	Stan Shebs	1	-1461/+0
1997-12-05	Reverrt BREAK value back to its old value	Nick Clifton	1	-1/+1
1997-12-04	Fixed sanitization,	Nick Clifton	1	-208/+64
1997-09-19	Clean up tracing for Bcond & jmp insns.	Andrew Cagney	1	-128/+100
1997-09-19	Fix cmov immed.	Andrew Cagney	1	-12/+56
1997-09-19	Fix cmov insn.	Andrew Cagney	1	-1/+3
1997-09-17	Clean up more tracing.	Andrew Cagney	1	-3/+21
1997-09-17	Fix tracing for: "ctret", "bsw", "hsw"	Andrew Cagney	1	-36/+72
1997-09-16	Smooth some of ALU tracing's rough edges.	Andrew Cagney	1	-39/+69
1997-09-16	Restrict ldsr (load system register) to modifying just non-reserved PSW bits.	Andrew Cagney	1	-2/+16
1997-09-16	Add v850e version of breakpoint instruction.	Andrew Cagney	1	-5/+16
1997-09-15	For instructions moved into v850.igen was computing (wrong) NIA when	Andrew Cagney	1	-10/+10
1997-09-15	Fix sanitization for v850 V v850e V v850eq	Andrew Cagney	1	-11/+267
1997-09-15	For v850eq start up with US bit set.	Andrew Cagney	1	-2/+26
1997-09-12	Check reserved bits before executing instructions.	Andrew Cagney	1	-1/+48
1997-09-08	Add multi-sim support to v850/v850e/v850eq simulators.	Andrew Cagney	1	-0/+1151