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path: root/sim/v850/sim-main.h
AgeCommit message (Expand)AuthorFilesLines
2023-01-18sim: v850: reduce extra header inclusion to igen filesMike Frysinger1-0/+4
2023-01-18sim: v850: drop redundant defineMike Frysinger1-4/+0
2022-12-23sim: v850: standardize the arch-specific settings a littleMike Frysinger1-715/+6
2022-12-22sim: move bfd.h include out of sim-main.hMike Frysinger1-2/+0
2022-12-21sim: enable common sim_cpu usage everywhereMike Frysinger1-2/+0
2022-12-21sim: v850: invert sim_cpu storageMike Frysinger1-12/+12
2022-11-03sim: v850: switch to standard (high-level) trace definesMike Frysinger1-1/+1
2022-01-06sim: v850: migrate to standard uintXX_t typesMike Frysinger1-25/+19
2021-05-17sim: fully merge sim_state_base into sim_stateMike Frysinger1-2/+0
2021-05-17sim: invert sim_state storageMike Frysinger1-12/+2
2021-05-16sim: switch config.h usage to defs.hMike Frysinger1-1/+0
2015-12-24sim: enable watchpoint module everywhereMike Frysinger1-5/+0
2015-11-17sim: mn10300/v850: drop unused WITH_CORE defineMike Frysinger1-1/+0
2015-11-17sim: always enable modulo memoryMike Frysinger1-1/+0
2015-04-18sim: unify SIM_CPU definitionMike Frysinger1-3/+0
2015-04-18sim: unify sim_cia definitionMike Frysinger1-2/+0
2015-04-17sim: replace CIA_{GET,SET} with CPU_PC_{GET,SET}Mike Frysinger1-3/+0
2015-04-15sim: unify sim-cpu usageMike Frysinger1-5/+0
2015-04-13sim: v850: convert to sim-cpuMike Frysinger1-3/+5
2015-02-27Fixes problems building the V850 simulator introduced with the previous delta.Nick Clifton1-1/+85
2014-01-07remove PARAMS from simTom Tromey1-3/+3
2012-03-29Commit gdb and sim support for v850e2 and v850e2v3 on behalf ofKevin Buettner1-2/+296
2002-11-302002-11-30 Andrew Cagney <cagney@redhat.com>Andrew Cagney1-2/+2
2002-08-29Makefile.in: Add gen-zero-r0 option.Nick Clifton1-0/+2
1999-04-16Initial creation of sourceware repositorygdb-4_18-branchpointStan Shebs1-0/+388
1999-04-16Initial creation of sourceware repositoryStan Shebs1-470/+0
1997-09-19Clean up tracing for Bcond & jmp insns.Andrew Cagney1-0/+41
1997-09-19Fix cmov immed.Andrew Cagney1-3/+17
1997-09-19Fix cmov insn.Andrew Cagney1-0/+17
1997-09-17Clean up more tracing.Andrew Cagney1-1/+1
1997-09-17Fix tracing for: "ctret", "bsw", "hsw"Andrew Cagney1-5/+52
1997-09-16Smooth some of ALU tracing's rough edges.Andrew Cagney1-5/+59
1997-09-16Restrict ldsr (load system register) to modifying just non-reserved PSW bits.Andrew Cagney1-0/+1
1997-09-15For instructions moved into v850.igen was computing (wrong) NIA whenAndrew Cagney1-4/+10
1997-09-15Fix sanitization for v850 V v850e V v850eqAndrew Cagney1-4/+31
1997-09-15For v850eq start up with US bit set.Andrew Cagney1-0/+52
1997-09-12Check reserved bits before executing instructions.Andrew Cagney1-0/+1
1997-09-12Add profiling support to v850*.Andrew Cagney1-0/+8
1997-09-08Add multi-sim support to v850/v850e/v850eq simulators.Andrew Cagney1-26/+51
1997-09-04Replace memory model with one from sim/common directory.Andrew Cagney1-9/+15
1997-09-03Pacify gcc-current -Wall.Andrew Cagney1-2/+1
1997-09-03Standard simulator header file.Andrew Cagney1-0/+172
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