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path: root/sim/v850/interp.c
AgeCommit message (Expand)AuthorFilesLines
2021-04-12sim: cgen: move cgen_cpu_max_extra_bytes logic into the common codeMike Frysinger1-1/+1
2021-02-06sim: watchpoints: use common sim_pc_getMike Frysinger1-1/+0
2021-01-30sim: watchpoints: change sizeof_pc to sizeof(sim_cia)Mike Frysinger1-1/+0
2021-01-11sim: clean up C11 header includesMike Frysinger1-9/+0
2016-01-06sim: sim_{create_inferior,open,parse_args}: constify argv/env slightlyMike Frysinger1-3/+3
2016-01-03sim: parse_args: display getopt error ourselvesMike Frysinger1-3/+1
2015-12-30sim: arm/d10v/h8300/m68hc11/microblaze/mips/mn10300/moxie/sh/v850: convert to...Mike Frysinger1-11/+10
2015-11-15sim: sim-close: unify sim_close logicMike Frysinger1-7/+0
2015-06-11sim: m68hc11/mn10300/v850: delete redundant INLINE definesMike Frysinger1-8/+0
2015-04-13sim: v850: convert to sim-cpuMike Frysinger1-6/+25
2015-03-24sim: m68hc11/mips/mn10300/v850: add basic sim_pc_getMike Frysinger1-0/+6
2015-02-27Fixes problems building the V850 simulator introduced with the previous delta.Nick Clifton1-32/+23
2013-01-28 * simops.c (v850_rotl): New function.Nick Clifton1-0/+1
2013-01-10 * interp.c (sim_open): Add support for bfd_arch_v850_rh850Nick Clifton1-1/+4
2011-07-05sim: start a unified sim_do_commandMike Frysinger1-19/+0
2011-01-11http://sourceware.org/ml/gdb-patches/2010-11/msg00112.htmlAndrew Burgess1-1/+1
2010-03-30sim: v850: fix build failure after watchpoint constificationMike Frysinger1-2/+2
2003-09-05Add support for v850e1 instructionsNick Clifton1-0/+1
2003-02-27Index: arm/ChangeLogAndrew Cagney1-2/+2
2002-09-19Remove v850ea referencesNick Clifton1-11/+0
1999-04-16Initial creation of sourceware repositorygdb-4_18-branchpointStan Shebs1-0/+360
1999-04-16Initial creation of sourceware repositoryStan Shebs1-357/+0
1998-02-28Add generic sim-info.c:sim_info() function using module mechanism.Andrew Cagney1-21/+17
1997-09-17Clean up more tracing.Andrew Cagney1-172/+78
1997-09-16Restrict ldsr (load system register) to modifying just non-reserved PSW bits.Andrew Cagney1-22/+26
1997-09-15For v850eq start up with US bit set.Andrew Cagney1-6/+7
1997-09-12Check reserved bits before executing instructions.Andrew Cagney1-0/+6
1997-09-12Add profiling support to v850*.Andrew Cagney1-8/+4
1997-09-10o Wordwrap usage messages from sim-optionsAndrew Cagney1-1/+3
1997-09-08Add multi-sim support to v850/v850e/v850eq simulators.Andrew Cagney1-339/+120
1997-09-04Replace memory model with one from sim/common directory.Andrew Cagney1-279/+31
1997-09-03Pacify gcc-current -Wall.Andrew Cagney1-15/+15
1997-09-03Add real SIM_DESC arg to v850 simulator.Andrew Cagney1-193/+179
1997-08-27Add ABFD argument to sim_create_inferior. Document.Andrew Cagney1-2/+6
1997-08-26Flush defunct sim_kill.Andrew Cagney1-7/+0
1997-08-25Add ABFD argument to sim_open call. Pass through to sim_config soAndrew Cagney1-159/+45
1997-04-18Ref gdb/11763 - can't stop a running simulator:Andrew Cagney1-0/+7
1997-04-17 * Makefile.in (SIM_OBJS): Add sim-load.o.David Edelsohn1-111/+640
1996-09-28 * gencode.c (write_opcodes): Output hex values for opcode maskStu Grossman1-4/+8
1996-09-11Add tracing support; Fix some problems with hardwired sizesMichael Meissner1-9/+20
1996-09-10 * interp.c (hash): Make this an inline functionJeff Law1-14/+28
1996-09-03Fix typpppoJeff Law1-1/+1
1996-09-03 * interp.c: OP should be an array of 32bit operands!Jeff Law1-13/+13
1996-08-30 * interp.c: Remove various debugging printfs.Jeff Law1-15/+0
1996-08-30 * interp.c (hash): Fix.Jeff Law1-18/+19
1996-08-30 * interp.c (do_format_4): Get operands correctly andJeff Law1-0/+6
1996-08-30 * v850_sim.h: The V850 doesn't have split I&D spaces. ChangeJeff Law1-61/+40
1996-08-30 * interp.c (do_format_5): Get operands correctly andJeff Law1-1/+7
1996-08-30 * interp.c (do_format_3): Get operands correctly and callJeff Law1-0/+5
1996-08-29 * interp.c (hash): Update to be more accurate.Jeff Law1-41/+115
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