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2016-01-10sim: drop --enable-sim-cflags optionMike Frysinger2-5/+4
No other sub directory provides such a configuration option, so drop it from the sim dir as well. This cleans up a good bit of code in the process. If people want to use custom flags for just the sim, they can still run configure+make by hand in the sim subdir and use the normal CFLAGS settings.
2016-01-06Change copyright owner to FSF in sim/testsuite/sim/mips/hilo-hazard-4.sJoel Brobecker2-2/+5
sim/testsuite/sim/mips/ChangeLog: * hilo-hazard-4.s: Change copyright ownder to FSF.
2016-01-05Fix the execution of the MSP430 simulator testsuite.Nick Clifton2-2/+38
ld * emulparams/msp430elf.sh (RAM_START): Move to 0x500 - above the MSP430 hardware multiply address range. * scripttempl/elf32msp430.sc (__romdatastart): Define. (__romdatacopysize): Define. * scripttempl/elf32msp430_3.sc: Likewise. tests * testutils.inc (__pass): Use the LMA addresses of the _passmsg symbol. (__fail): Likewise.
2016-01-04sim: parse_args: polish getopt error messageMike Frysinger3-2/+7
The cris sim hit a few failures after the recent getopt logic, and the expected output showed a few ways we can improve things to better match other utils.
2016-01-03sim: convert to bfd_endianMike Frysinger2-1/+6
Rather than re-invent endian defines, as well as maintain our own list of OS & arch-specific includes, punt all that logic in favor of the bfd ones already set up and maintained elsewhere. We already rely on the bfd library, so leveraging the endian aspect should be fine.
2016-01-01GDB copyright headers update after running GDB's copyright.py script.Joel Brobecker19-19/+19
gdb/ChangeLog: Update year range in copyright notice of all files.
2015-12-25sim: cris: migrate from WITH_DEVICES to WITH_HWMike Frysinger2-1/+5
The cris port was using the device framework to handle two addresses when the --cris-900000xx flag was specified. That can be implemented using the newer hardware framework instead which allows us to drop the device logic entirely, as well as delete the tconfig.h file. Basically we create a new cris_900000xx device model and move the read logic out of devices.c and into that. The rest of the devices logic was callback to the hardware framework already.
2015-12-25sim: cris: set up sane default path to rvdummyMike Frysinger2-1/+14
Much like we autodetect the path to the run program when there is none set explicitly, do the same for the rvdummy program. Otherwise the default make check fails to execute the helper properly.
2015-12-24sim: make LMA loading the default for all targetsMike Frysinger3-1/+25
Most targets already default to loading code via their LMA, but for a few, this means the default changes from loading VMA to LMA. It's better to have the different targets be consistent, and allows some code clean up.
2015-11-24Add an AArch64 simulator to GDB.Nick Clifton6-0/+105
sim * configure.tgt: Add aarch64 entry. * configure: Regenerate. * sim/aarch64/configure.ac: New configure template. * sim/aarch64/aclocal.m4: Generate. * sim/aarch64/config.in: Generate. * sim/aarch64/configure: Generate. * sim/aarch64/cpustate.c: New file - functions for accessing AArch64 registers. * sim/aarch64/cpustate.h: New header. * sim/aarch64/decode.h: New header. * sim/aarch64/interp.c: New file - interface between GDB and simulator. * sim/aarch64/Makefile.in: New makefile template. * sim/aarch64/memory.c: New file - functions for simulating aarch64 memory accesses. * sim/aarch64/memory.h: New header. * sim/aarch64/sim-main.h: New header. * sim/aarch64/simulator.c: New file - aarch64 simulator functions. * sim/aarch64/simulator.h: New header. include/gdb * sim-aarch64.h: New file. sim/test * configure: Regenerate. * sim/aarch64: New directory.
2015-11-15sim: mcore: add a fail testcaseMike Frysinger3-1/+14
2015-11-15sim: m32c: add a basic testsuiteMike Frysinger5-0/+92
2015-11-15sim: testsuite: support basic vars in flagsMike Frysinger2-1/+12
Sometimes in tests, we need supplemental files like linker scripts or board helper files. There's no way to set those flags in the tests currently and relative paths don't work (breaks out of tree builds). Update the main option parser to replace some strings on the fly. Now tests can do things like: Long term we'll want to switch the framework to use the dejagnu helpers like dg-xxx that gcc & gdb utilize. But that'll require more rework.
2015-11-10sim: m32c: move test code to testsuiteMike Frysinger6-0/+167
Various target code belongs in the testsuite/ subdir, so move the m32c code to match all the other targets.
2015-10-12sim: ft32: test coverage for link parameters and PM write portJames Bowman2-0/+42
Adds test coverage for recent features.
2015-10-11sim: bfin: handle negative left saturated shifts as ashifts [BZ #18407]Mike Frysinger2-0/+22
When handling left saturated ashifts with negative immediates, they should be treated as right ashifts. This matches hardware behavior. Reported-by: Igor Rayak <igorr@gitatechnologies.com>
2015-09-25[PATCH] Add micromips support to the MIPS simulatorAndrew Bennett4-6/+77
2015-09-25 Andrew Bennett <andrew.bennett@imgtec.com> Ali Lown <ali.lown@imgtec.com> sim/common/ * sim-bits.h (EXTEND6): New macro. (EXTEND12): New macro. (EXTEND25): New macro. sim/mips/ * Makefile.in (tmp-micromips): New rule. (tmp-mach-multi): Add support for micromips. * configure.ac (mips*-sde-elf* | mips*-mti-elf*): Made a multi sim that works for both mips64 and micromips64. (mipsisa32r2*-*-*): Made a multi sim that works for mips32 and micromips32. Add build support for micromips. * dsp.igen (do_ph_s_absq, do_w_s_absq, do_qb_s_absq, do_addsc, do_addwc, do_bitrev, do_extpv, do_extrv, do_extrv_s_h, do_insv, do_lxx do_modsub, do_mthlip, do_mulsaq_s_w_ph, do_ph_packrl, do_qb_pick do_ph_pick, do_qb_ph_precequ, do_qb_ph_preceu, do_w_preceq do_w_ph_precrq, do_ph_qb_precrq, do_w_ph_rs_precrq do_qb_w_raddu, do_rddsp, do_repl, do_shilov, do_ph_shl, do_qb_shl do_w_s_shllv, do_ph_shrlv, do_w_r_shrav, do_wrdsp, do_qb_shrav, do_append, do_balign, do_ph_w_mulsa, do_ph_qb_precr, do_prepend): New functions. Refactored instruction code to use these functions. * dsp2.igen: Refactored instruction code to use the new functions. * interp.c (decode_coproc): Refactored to work with any instruction encoding. (isa_mode): New variable (RSVD_INSTRUCTION): Changed to 0x00000039. * m16.igen (BREAK16): Refactored instruction to use do_break16. (JALX32): Add mips32, mips64, mips32r2 and mips64r2 models. * micromips.dc: New file. * micromips.igen: New file. * micromips16.dc: New file. * micromipsdsp.igen: New file. * micromipsrun.c: New file. * mips.igen (do_swc1): Changed to work with any instruction encoding. (do_add do_addi do_andi do_dadd do_daddi do_dsll32 do_dsra32 do_dsrl32, do_dsub, do_break, do_break16, do_clo, do_clz, do_dclo do_dclz, do_lb, do_lh, do_lwr, do_lwl, do_lwc, do_lw, do_lwu, do_lhu do_ldc, do_lbu, do_ll, do_lld, do_lui, do_madd, do_dsp_madd, do_maddu do_dsp_maddu, do_dsp_mfhi, do_dsp_mflo, do_movn, do_movz, do_msub do_dsp_msub, do_msubu, do_dsp_msubu, do_mthi, do_dsp_mthi, do_mtlo do_dsp_mtlo, do_mul, do_dsp_mult, do_dsp_multu, do_pref, do_sc, do_scd do_sub, do_sw, do_teq, do_teqi, do_tge, do_tgei, do_tgeiu, do_tgeu, do_tlt do_tlti, do_tltiu, do_tltu, do_tne, do_tnei, do_abs_fmt, do_add_fmt do_alnv_ps, do_c_cond_fmt, do_ceil_fmt, do_cfc1, do_ctc1, do_cvt_d_fmt do_cvt_l_fmt, do_cvt_ps_s, do_cvt_s_fmt, do_cvt_s_pl, do_cvt_s_pu do_cvt_w_fmt, do_div_fmt, do_dmfc1b, do_dmtc1b, do_floor_fmt, do_luxc1_32 do_luxc1_64, do_lwc1, do_lwxc1, do_madd_fmt, do_mfc1b, do_mov_fmt, do_movtf do_movtf_fmt, do_movn_fmt, do_movz_fmt, do_msub_fmt, do_mtc1b, do_mul_fmt do_neg_fmt, do_nmadd_fmt, do_nmsub_fmt, do_pll_ps, do_plu_ps, do_pul_ps do_puu_ps, do_recip_fmt, do_round_fmt, do_rsqrt_fmt, do_prefx, do_sdc1 do_suxc1_32, do_suxc1_64, do_sqrt_fmt, do_sub_fmt, do_swc1, do_swxc1 do_trunc_fmt): New functions, refactored from existing instructions. Refactored instruction code to use these functions. (RSVD): Changed to use new reserved instruction. (loadstore_ea, not_word_value, unpredictable, check_mt_hilo, check_mf_hilo, check_mult_hilo, check_div_hilo, check_u64, do_luxc1_32, do_sdc1, do_suxc1_32, check_fmt_p, check_fpu, do_load_double, do_store_double): Added micromips32 and micromips64 models. Added include for micromips.igen and micromipsdsp.igen Add micromips32 and micromips64 models. (DecodeCoproc): Updated to use new macro definition. * mips3264r2.igen (do_dsbh, do_dshd, do_dext, do_dextm, do_dextu, do_di, do_dins, do_dinsm, do_ei, do_ext, do_mfhc1, do_mthc1, do_ins, do_dinsu, do_seb, do_seh do_rdhwr, do_wsbh): New functions. Refactored instruction code to use these functions. * sim-main.h (CP0_operation): New enum. (DecodeCoproc): Updated macro. (IMEM32_MICROMIPS, IMEM16_MICROMIPS, MICROMIPS_MINOR_OPCODE, MICROMIPS_DELAYSLOT_SIZE_ANY, MICROMIPS_DELAYSLOT_SIZE_16, MICROMIPS_DELAYSLOT_SIZE_32, ISA_MODE_MIPS32 and ISA_MODE_MICROMIPS): New defines. (sim_state): Add isa_mode field. sim/testsuite/sim/mips/ * basic.exp (run_micromips_test, run_sim_tests): New functions Add support for micromips tests. * hilo-hazard-4.s: New file. * testutils.inc (_dowrite): Changed reserved instruction encoding. (writemsg): Moved the la and li instructions before the data they are assigned to, which prevents a bug where MIPS32 relocations are used instead of micromips relocations when building for micromips.
2015-07-24Remove leading/trailing white spaces in ChangeLogH.J. Lu7-25/+25
2015-04-13Do unset_currtarget_info ldscript for all simulator testsuites.Hans-Peter Nilsson4-6/+18
sim/testsuite: * sim-defs.exp (sim_init): Unset target ldscript here. sim/testsuite/sim/mips: * basic.exp: Don't unset target ldscript here.
2015-04-05sim: moxie: fix running after nrun conversionMike Frysinger4-0/+71
The nrun conversion was slightly incorrect in how it stopped when an exception occurred. We still set cpu.asregs.exception, but nothing was checking it anymore. Convert all of that to sim_engine_halt. To keep things from regressing again, add a basic testsuite too.
2015-04-05sim: mn10300: add a basic testsuiteMike Frysinger4-0/+88
2015-04-05sim: m68hc11: add a basic testsuiteMike Frysinger4-0/+78
2015-04-05sim: iq2000: add a basic testsuiteMike Frysinger4-0/+78
2015-04-05sim: lm32: add a basic testsuiteMike Frysinger4-0/+84
2015-03-30sim: d10v: convert to nrunMike Frysinger2-1/+5
A lot of cpu state is stored in global variables, as is memory handling. The sim_size support needs unwinding at some point. But at least this is an improvement on the status quo.
2015-03-30sim: d10v: link in missing testsuiteMike Frysinger3-3/+16
Looks like historical restructuring in this dir lost the d10v-elf subdir and no one noticed in the meantime. Re-add it to the testsuite. There are some failures, but better some tests get run than none at all.
2015-03-29sim: cr16: add _start symbol to tests [BZ #12385]Mike Frysinger2-0/+7
The current cr16 testsuite sets up _START, but the linker looks for the _start symbol. Add the latter as an alias to the former.
2015-03-29sim: microblaze: start a testsuiteMike Frysinger4-0/+55
Since the sim doesn't have any debug support in it, we can only exit cleanly. But this is still better than nothing. Change the default microblaze sim to not dump the debug load output when running. No other does this, and it breaks the testsuite.
2015-03-29sim; testsuite: allow tests to set no outputMike Frysinger2-1/+9
If a test doesn't write anything at all to stdout, the current test framework can't support that. Even if you put a blank output line: # output: the setup happily clobbers that with a default pass/fail string. Tweak the parsing logic so we only set the output to pass/fail when the test has no output marker.
2015-03-29sim: testsuite: make subdir unconditionalMike Frysinger2-22/+4
Since the testsuite subdir has to handle dynamic arch values already, there's no real value in requiring arches to opt in to it. Most have a testsuite now anyways, and we're requiring it in the future.
2015-03-29sim: mcore: add a basic testsuiteMike Frysinger4-0/+77
2015-03-29sim: avr: fix _start testsuite symbolMike Frysinger2-1/+6
Make sure we use the symbol the linker expects by default, and we export it so it can be found.
2015-03-28sim: avr: start a basic testsuiteMike Frysinger6-0/+71
Just enough to know the sim isn't totally broken.
2015-03-28sim: ft32: new portJames Bowman6-0/+953
FT32 is a new high performance 32-bit RISC core developed by FTDI for embedded applications.
2015-01-01Update year range in copyright notice of all files owned by the GDB project.Joel Brobecker14-14/+14
gdb/ChangeLog: Update year range in copyright notice of all files.
2014-03-10sim: msp430: start a test frameworkMike Frysinger6-0/+113
The current sim lacks any sort of tests. Start a basic framework and add a simple one to test the add insn.
2014-03-04sim: convert old style prototypesMike Frysinger2-5/+7
Most of these prototypes have been killed off, but we have a few left in the sim tree. Clean them up so we can enable the -W flag for it.
2014-01-01Update Copyright year range in all files maintained by GDB.Joel Brobecker14-14/+14
2013-12-07sim: bfin: tests: make run-tests.sh executableMike Frysinger2-0/+4
I meant for this script to be +x, but missed when doing the initial CVS commit. It wasn't possible to fix w/CVS, but it is w/git, so do it. Signed-off-by: Mike Frysinger <vapier@gentoo.org> 2012-12-03 Mike Frysinger <vapier@gentoo.org> * run-tests.sh: Add +x file mode.
2013-09-23Regenerate sim configure files to pick up support for powerpc64le inAlan Modra2-0/+7
libtool.m4.
2013-06-24sim: bfin: run-tests.sh: fix typo in usage exitMike Frysinger2-1/+5
2013-06-24sim: bfin: se_all32bitopcodes: skip debug insns under the simMike Frysinger2-1/+18
Since the sim has a few fake debug insns that the hardware does not, we need to check for those before attempting to run them. Otherwise we'll randomly trigger the sim debug asserts/aborts/halts insns. On the hardware, these are proper invalid insns, and the table catches that.
2013-06-24sim: bfin: speed up all insn testcases slightlyMike Frysinger2-2/+8
The main body of the "all insn" test is executed once per tested insn, and we test millions of insns here. Any shrinkage we can do in this loop will speed things up nicely (since it's multiplied per tested insn). To that end, simplify the end-of-table test into one less insn, and omit the SSYNC when we build for the sim. When we build to run on the hardware, this insn matters, but the sim doesn't have write store buffers in the chip that might get in the way (memory writes are atomic).
2013-06-23sim: bfin: trim trailing whitespaceMike Frysinger2-1/+5
2013-06-17sim: bfin: tweak run-tests for parallel usageMike Frysinger2-6/+34
2013-06-17sim: bfin: add helpful info for generating test tablesMike Frysinger2-0/+23
2013-06-17sim: bfin: drop RET[ENI] setupMike Frysinger2-3/+4
Since these insns run in usermode, there should be no need to setup RET[ENI] to safe values. They won't be dereferenced, and any insn that returns via them are valid only in supervisor mode. Since this is in the main exception code path, saving any insn at all is good as it gets multiplied quickly (as in O(n^2) times). Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2013-05-15sim: arm: add support for MOVW and MOVT instructionsMike Frysinger2-0/+58
From: Jayant R. Sonar <Jayant.Sonar@kpitcummins.com> This patch adds simulator support for handling the armv7 instructions 'movw (immediate)' and 'movt'. Compiler frequently use these instructions to load the 32bit addresses of global variables, string pointers etc. into the general registers. In absence of support of these instructions: 1. GDB run simulator fails to print even simple "hello world" string on console. 2. Loading of global variable addresses into the registers fail causing arithmetic operation failures. Patch has been regression tested for arm-none-eabi (-march=armv7-a).
2013-01-01Update years in copyright notice for the GDB files.Joel Brobecker14-14/+14
Two modifications: 1. The addition of 2013 to the copyright year range for every file; 2. The use of a single year range, instead of potentially multiple year ranges, as approved by the FSF.
2012-12-19[sim] Update old contact info in GPL license noticesJoel Brobecker1-2/+1
sim/ChangeLog: Update old contact info in GPL license notices.
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