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path: root/sim/testsuite/d10v-elf/ChangeLog
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2015-07-24Remove leading/trailing white spaces in ChangeLogH.J. Lu1-3/+3
2015-03-30sim: d10v: convert to nrunMike Frysinger1-0/+4
2009-08-22Regenerate tree using Autoconf 2.64 and Automake 1.11.Ralf Wildenhues1-0/+4
2005-01-10Index: arm/ChangeLogAndrew Cagney1-0/+5
2000-04-18Add support for SIGILL (reserved-instruction-exception).Andrew Cagney1-0/+5
2000-02-22When SIM_HAVE_ENVIRONMENT: use sim_set_trace() to enable tracingAndrew Cagney1-0/+4
2000-01-06import gdb-2000-01-05 snapshotJason Molenda1-0/+12
1999-11-17import gdb-1999-11-16 snapshotJason Molenda1-0/+9
1999-09-13import gdb-1999-09-13 snapshotJason Molenda1-0/+7
1999-04-16Initial creation of sourceware repositorygdb-4_18-branchpointStan Shebs1-0/+84
1999-04-16Initial creation of sourceware repositoryStan Shebs1-66/+0
1998-02-13Test switching between SPI/SPU.Andrew Cagney1-0/+5
1998-02-11Update tests to match recently modified ABIAndrew Cagney1-0/+11
1997-12-08Fix typo, REP_S was refering to REP_E register.Andrew Cagney1-0/+4
1997-12-08For "trap", IBT and RIE exceptions, mask all PSW.SM. NB: SteppingAndrew Cagney1-0/+7
1997-12-04Add DM (bit 4) to PSW. See 7-1 for more info.Andrew Cagney1-0/+7
1997-12-03* d10v_sim.h (SEXT56): Define.Andrew Cagney1-1/+10
1997-12-02For "msbu", subtract unsigned product from ACC,Andrew Cagney1-1/+1
1997-12-02For "mulxu", store unsigned product in ACC.Andrew Cagney1-1/+2
1997-12-02For sub2w, compute carry according to negated addition rules.Andrew Cagney1-0/+14
1997-11-10Test rachi instruction.Andrew Cagney1-0/+8
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