riscv-gnu-toolchain/gdb.git - Unnamed repository; edit this file 'description' to name the repository.

Age	Commit message (Expand)	Author	Files	Lines
2009-08-22	Regenerate tree using Autoconf 2.64 and Automake 1.11.	Ralf Wildenhues	1	-0/+4
2005-01-10	Index: arm/ChangeLog	Andrew Cagney	1	-0/+5
2000-04-18	Add support for SIGILL (reserved-instruction-exception).	Andrew Cagney	1	-0/+5
2000-02-22	When SIM_HAVE_ENVIRONMENT: use sim_set_trace() to enable tracing	Andrew Cagney	1	-0/+4
2000-01-06	import gdb-2000-01-05 snapshot	Jason Molenda	1	-0/+12
1999-11-17	import gdb-1999-11-16 snapshot	Jason Molenda	1	-0/+9
1999-09-13	import gdb-1999-09-13 snapshot	Jason Molenda	1	-0/+7
1999-04-16	Initial creation of sourceware repositorygdb-4_18-branchpoint	Stan Shebs	1	-0/+84
1999-04-16	Initial creation of sourceware repository	Stan Shebs	1	-66/+0
1998-02-13	Test switching between SPI/SPU.	Andrew Cagney	1	-0/+5
1998-02-11	Update tests to match recently modified ABI	Andrew Cagney	1	-0/+11
1997-12-08	Fix typo, REP_S was refering to REP_E register.	Andrew Cagney	1	-0/+4
1997-12-08	For "trap", IBT and RIE exceptions, mask all PSW.SM. NB: Stepping	Andrew Cagney	1	-0/+7
1997-12-04	Add DM (bit 4) to PSW. See 7-1 for more info.	Andrew Cagney	1	-0/+7
1997-12-03	* d10v_sim.h (SEXT56): Define.	Andrew Cagney	1	-1/+10
1997-12-02	For "msbu", subtract unsigned product from ACC,	Andrew Cagney	1	-1/+1
1997-12-02	For "mulxu", store unsigned product in ACC.	Andrew Cagney	1	-1/+2
1997-12-02	For sub2w, compute carry according to negated addition rules.	Andrew Cagney	1	-0/+14
1997-11-10	Test rachi instruction.	Andrew Cagney	1	-0/+8