aboutsummaryrefslogtreecommitdiff
path: root/sim/sh
AgeCommit message (Expand)AuthorFilesLines
2023-01-11sim: build: drop subdir Makefile.in filesMike Frysinger1-19/+0
2023-01-10sim: move arch-specific file compilation of common/ files to top-levelMike Frysinger1-2/+2
2023-01-10sim: sh: move arch-specific file compilation to top-levelMike Frysinger1-3/+0
2023-01-10sim: build: drop support for creating libsim.a in subdirsMike Frysinger1-3/+0
2023-01-10sim: sh: move libsim.a creation to top-levelMike Frysinger2-4/+19
2023-01-10sim: modules: trigger generation from top-levelMike Frysinger1-0/+1
2023-01-02sim: sh: move some generated source files to built sourcesMike Frysinger1-2/+6
2023-01-01Update copyright year range in header of all files managed by GDBJoel Brobecker4-4/+4
2022-12-25sim: cpu: change default init to handle all cpusMike Frysinger1-1/+1
2022-12-23sim: sh: move arch-specific settings to internal headerMike Frysinger3-96/+120
2022-12-22sim: switch sim_{read,write} APIs to 64-bit all the time [PR sim/7504]Mike Frysinger1-4/+4
2022-12-21sim: enable common sim_cpu usage everywhereMike Frysinger1-2/+0
2022-12-20sim: sim_cpu: invert sim_cpu storageMike Frysinger1-5/+2
2022-12-20sim: move register headers into sim/ namespace [PR sim/29869]Mike Frysinger1-1/+1
2022-11-05sim: run: move linking into top-levelMike Frysinger1-0/+8
2022-11-04sim: build: remove various obsolete generation dep variablesMike Frysinger1-1/+0
2022-11-04sim: drop -lm from SIM_EXTRA_LIBSMike Frysinger1-1/+0
2022-11-02sim: common: change sim_{fetch,store}_register helpers to use void* buffersMike Frysinger1-2/+2
2022-10-31sim: reg: constify store helperMike Frysinger1-1/+1
2022-10-31sim: common: change sim_read & sim_write to use void* buffersMike Frysinger1-5/+7
2022-10-29sim/sh: Remove redundant function declarationTsukasa OI1-2/+0
2022-10-24sim/sh: use fabs instead of absAndrew Burgess1-1/+1
2022-01-01Automatic Copyright Year update after running gdb/copyright.pyJoel Brobecker3-3/+3
2021-12-09sim: use ## for automake commentsMike Frysinger1-18/+18
2021-11-28sim: sh: switch to new target-newlib-syscallMike Frysinger2-25/+23
2021-11-15sim: split program path out of argv vectorMike Frysinger1-4/+1
2021-11-13sim: sh: fix switch-bool warningsMike Frysinger1-51/+28
2021-11-13sim: sh: rework carry checks to not rely on integer overflowsMike Frysinger1-4/+4
2021-11-06sim: sh: fix conversion of PC to an integerMike Frysinger1-1/+1
2021-11-06sim: sh: clean up time(NULL) callMike Frysinger1-1/+1
2021-11-06sim: sh: break utime logic out of _WIN32 checkMike Frysinger1-1/+8
2021-11-06sim: sh: drop errno externMike Frysinger1-1/+0
2021-11-06sim: sh: fix isnan redefinition with mingw targetsMike Frysinger1-0/+2
2021-11-06sim: sh: enable -Werror everywhereMike Frysinger1-3/+0
2021-11-06sim: sh: fix uninitialized variable usage with pdmsbMike Frysinger1-1/+1
2021-11-06sim: sh: constify a few read-only lookup tablesMike Frysinger1-6/+6
2021-11-06sim: sh: fix various parentheses warningsMike Frysinger2-11/+11
2021-11-06sim: sh: fix unused-value warningsMike Frysinger1-3/+3
2021-11-06sim: sh: rework register layout with anonymous unions & structsMike Frysinger3-90/+82
2021-11-02sim: hoist gencode & opc2c build rules up to common buildsMike Frysinger2-21/+48
2021-11-01sim: sh: reduce -Wno-error scopeMike Frysinger1-2/+2
2021-10-31sim: tighten up gencode outputMike Frysinger1-5/+5
2021-08-17sim: rename ChangeLog files to ChangeLog-2021Mike Frysinger1-0/+0
2021-06-22sim: drop configure scripts for simple portsMike Frysinger4-2893/+6
2021-06-21sim: unify hardware settingsMike Frysinger3-54/+5
2021-06-21sim: hw: rework configure option & device selectionMike Frysinger2-38/+30
2021-06-20sim: delete SIM_AC_COMMON macroMike Frysinger4-5/+5
2021-06-20sim: unify general maintainer settingsMike Frysinger2-124/+0
2021-06-20sim: move sim-inline to the common codeMike Frysinger3-36/+5
2021-06-19sim: unify gettext/intl probing logicMike Frysinger2-85/+0
generated by cgit v1.1 at 2024-12-20 16:17:22 +0000