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path: root/sim/sh/interp.c
AgeCommit message (Expand)AuthorFilesLines
2023-01-16sim: assume sys/stat.h always exists (via gnulib)Mike Frysinger1-2/+0
2023-01-16sim: formally assume unistd.h always exists (via gnulib)Mike Frysinger1-2/+0
2022-12-25sim: cpu: change default init to handle all cpusMike Frysinger1-1/+1
2022-12-23sim: sh: move arch-specific settings to internal headerMike Frysinger1-0/+2
2022-12-22sim: switch sim_{read,write} APIs to 64-bit all the time [PR sim/7504]Mike Frysinger1-4/+4
2022-12-20sim: move register headers into sim/ namespace [PR sim/29869]Mike Frysinger1-1/+1
2022-11-02sim: common: change sim_{fetch,store}_register helpers to use void* buffersMike Frysinger1-2/+2
2022-10-31sim: reg: constify store helperMike Frysinger1-1/+1
2022-10-31sim: common: change sim_read & sim_write to use void* buffersMike Frysinger1-5/+7
2022-10-29sim/sh: Remove redundant function declarationTsukasa OI1-2/+0
2022-10-24sim/sh: use fabs instead of absAndrew Burgess1-1/+1
2021-11-28sim: sh: switch to new target-newlib-syscallMike Frysinger1-22/+23
2021-11-15sim: split program path out of argv vectorMike Frysinger1-4/+1
2021-11-13sim: sh: fix switch-bool warningsMike Frysinger1-51/+28
2021-11-06sim: sh: fix conversion of PC to an integerMike Frysinger1-1/+1
2021-11-06sim: sh: clean up time(NULL) callMike Frysinger1-1/+1
2021-11-06sim: sh: break utime logic out of _WIN32 checkMike Frysinger1-1/+8
2021-11-06sim: sh: drop errno externMike Frysinger1-1/+0
2021-11-06sim: sh: fix isnan redefinition with mingw targetsMike Frysinger1-0/+2
2021-11-06sim: sh: fix various parentheses warningsMike Frysinger1-2/+2
2021-11-06sim: sh: rework register layout with anonymous unions & structsMike Frysinger1-54/+54
2021-06-12sim: overhaul alignment settings managementMike Frysinger1-0/+3
2021-05-29sim: sh: fix a few compiler warningsMike Frysinger1-2/+2
2021-05-16sim: switch config.h usage to defs.hMike Frysinger1-1/+2
2021-05-14sim: create header namespaceMike Frysinger1-2/+2
2021-04-22Do not check for sys/time.h or sys/times.hTom Tromey1-2/+0
2021-04-18sim: sh: switch syscalls to common nltvalsMike Frysinger1-23/+22
2021-04-12sim: cgen: move cgen_cpu_max_extra_bytes logic into the common codeMike Frysinger1-1/+1
2021-01-11sim: clean up C11 header includesMike Frysinger1-12/+0
2017-02-13sim: use ARRAY_SIZE instead of ad-hoc sizeof calculationsMike Frysinger1-1/+1
2016-04-10Fix primary reason why the SH simulation hasn't been working on 64 bit hosts.Oleg Endo1-34/+12
2016-04-09Adjust default memory size and stack base address for SH simulator.Oleg Endo1-3/+3
2016-01-06sim: sim_{create_inferior,open,parse_args}: constify argv/env slightlyMike Frysinger1-2/+4
2016-01-03sim: parse_args: display getopt error ourselvesMike Frysinger1-3/+1
2016-01-03sim: use libiberty countargv in more placesMike Frysinger1-17/+3
2016-01-03sim: drop host endian configure optionMike Frysinger1-1/+1
2016-01-03sim: convert to bfd_endianMike Frysinger1-2/+2
2015-12-30sim: arm/d10v/h8300/m68hc11/microblaze/mips/mn10300/moxie/sh/v850: convert to...Mike Frysinger1-4/+6
2015-11-22sim: sh: delete global callback/argvMike Frysinger1-44/+35
2015-11-15sim: sim-close: unify sim_close logicMike Frysinger1-6/+0
2015-04-17sim: arm/cr16/d10v/h8300/microblaze/sh: fill out sim-cpu pc fetch/store helpersMike Frysinger1-0/+21
2015-03-28sim: sh: convert to nrunMike Frysinger1-204/+74
2015-03-28sim: sh: clean up some warningsMike Frysinger1-209/+98
2014-03-10sim: constify arg to sim_do_commandMike Frysinger1-4/+4
2014-03-05sim: constify prog_nameMike Frysinger1-1/+1
2014-02-17sim: delete duplicate SIGINT handlingMike Frysinger1-13/+0
2014-01-07remove PARAMS from simTom Tromey1-16/+16
2013-03-15gdb:Steve Ellcey1-1/+1
2012-02-16Update sim_fetch_register, sim_store_register for sh and mn10300.Kevin Buettner1-3/+3
2011-04-16sim: add sim_complete_command stubs for non-common-using portsMike Frysinger1-0/+6
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