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path: root/sim/riscv/sim-main.c
AgeCommit message (Expand)AuthorFilesLines
2023-12-22sim: riscv: fix -Wshadow=local warningsMike Frysinger1-6/+4
2023-12-21sim: riscv: fix -Wimplicit-fallthrough warningsMike Frysinger1-0/+1
2023-10-18sim/riscv: fix JALR instruction simulationJaydeep Patil1-1/+1
2023-01-01Update copyright year range in header of all files managed by GDBJoel Brobecker1-1/+1
2022-12-23sim: riscv: move arch-specific settings to internal headerMike Frysinger1-0/+2
2022-12-21sim: riscv: invert sim_cpu storageMike Frysinger1-187/+252
2022-12-20sim: move register headers into sim/ namespace [PR sim/29869]Mike Frysinger1-1/+1
2022-11-02sim: common: change sim_{fetch,store}_register helpers to use void* buffersMike Frysinger1-2/+2
2022-10-31sim: reg: constify store helperMike Frysinger1-1/+1
2022-10-31sim: common: change sim_read & sim_write to use void* buffersMike Frysinger1-5/+5
2022-10-11sim/riscv: fix multiply instructions on simulatorTsukasa OI1-0/+1
2022-09-05sim/riscv: Complete tidying up with SBREAKTsukasa OI1-3/+3
2022-01-06sim: riscv: migrate to standard uintXX_t typesMike Frysinger1-28/+28
2022-01-01Automatic Copyright Year update after running gdb/copyright.pyJoel Brobecker1-1/+1
2021-10-31sim: drop unused targ-vals.h includesMike Frysinger1-2/+0
2021-06-18sim: split sim-signal.h include outMike Frysinger1-0/+1
2021-05-17sim: riscv: invert sim_state storageMike Frysinger1-6/+7
2021-05-16sim: switch config.h usage to defs.hMike Frysinger1-1/+2
2021-05-16sim: riscv: move __int128 check to configureMike Frysinger1-1/+1
2021-05-01sim: riscv: fix building on 32-bit hosts w/out int128Mike Frysinger1-1/+1
2021-04-26sim: riscv: switch MIN/MAX to common min/maxMike Frysinger1-7/+4
2021-02-19RISC-V: PR27158, fixed UJ/SB types and added CSS/CL/CS types for .insn.Nelson Chu1-3/+3
2021-02-04gdb: riscv: enable sim integrationMike Frysinger1-0/+70
2021-02-04sim: riscv: new portMike Frysinger1-0/+1150
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