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AgeCommit message (Expand)AuthorFilesLines
2021-05-04sim: add support for build-time ar & ranlibMike Frysinger2-2/+14
2021-05-01sim: nrun: add local strsignal prototypeMike Frysinger3-2/+12
2021-04-26sim: nltvals: unify common syscall tablesMike Frysinger2-2/+4
2021-04-26sim: enable hardware support by defaultMike Frysinger4-5/+120
2021-04-22Do not check for sys/time.h or sys/times.hTom Tromey3-14/+6
2021-04-22Require GNU makeTom Tromey2-67/+6
2021-04-21sim: regen against sim/m4/Mike Frysinger2-9/+13
2021-04-21sim: use -Werror when probing for supported warning flagsSimon Marchi2-1/+5
2021-04-18sim: switch to AC_CHECK_HEADERS_ONCEMike Frysinger1-52/+47
2021-04-18sim: switch to AC_CHECK_FUNCS_ONCE & merge a littleMike Frysinger2-25/+52
2021-04-12sim: cgen: move cgen_cpu_max_extra_bytes logic into the common codeMike Frysinger2-1/+5
2021-04-02sim: unify toolchain settingsMike Frysinger3-153/+162
2021-02-28sim: set up build-time compiler settingsMike Frysinger1-9/+10
2021-02-28sim: use AC_CHECK_TOOL to find arMike Frysinger1-3/+93
2021-02-28sim: require AC_PROG_CPP explicitlyMike Frysinger2-140/+145
2021-02-21sim: common: split up acinclude.m4 into individual m4 filesMike Frysinger4-11/+34
2021-02-13sim: switch to AC_CONFIG_MACRO_DIRSMike Frysinger4-1834/+35
2021-02-06sim: common: switch AC_CONFIG_HEADERSMike Frysinger1-3/+2
2021-02-06sim: drop use of bfd/configure.hostMike Frysinger2-7/+15
2021-01-11sim: clean up C11 header includesMike Frysinger3-16/+35
2021-01-09sim: clean up stale AC_PREREQ refsMike Frysinger3-15/+8
2021-01-09sim: enable -Werror by default for some archesMike Frysinger2-5/+7
2021-01-09sim: pru: fix include ordering with sim-main.hMike Frysinger2-0/+6
2021-01-08sim: require a C11 compilerMike Frysinger2-13/+57
2021-01-04sim: update bug URI to https://Mike Frysinger2-1/+5
2021-01-01Update copyright year range in all GDB filesJoel Brobecker6-6/+6
2020-11-12sim: pru: Add support for LMBD instructionDimitar Dimitrov3-0/+23
2020-01-01Update copyright year range in all GDB files.Joel Brobecker6-6/+6
2019-09-23sim: Add PRU simulator portDimitar Dimitrov10-0/+17709
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