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2009-01-12 * ppc-instructions (sync): Add L field.Nathan Froyd1-1/+1
2008-12-152008-12-15 Joel Sherrill <joel.sherrill@oarcorp.com>Joel Sherrill1-0/+8
* ppc-instructions, ppc-spr-table: Add ability to read tbrl and tbru special registers.
2006-11-292006-11-22 Tom Marn <tom.marn@telargo.com>Andrew Cagney1-7/+12
Committed by Andrew Cagney. * ppc-instructions: Implement optional PowerPC stfiwx instruction.
2004-01-272004-01-27 Andrew Cagney <cagney@redhat.com>Andrew Cagney1-2/+2
* ppc-instructions: Update copyright. (convert_to_integer): Add trailing ";" to label.
2003-06-222003-06-22 Andrew Cagney <cagney@redhat.com>Andrew Cagney1-0/+20
Written by matthew green <mrg@redhat.com>, with fixes from Aldy Hernandez <aldyh@redhat.com>, Jim Wilson <wilson@redhat.com>, and Nick Clifton <nickc@redhat.com>. * ppc-instructions: Include altivec.igen and e500.igen. (model_busy, model_data): Add vr_busy and vscr_busy. (model_trace_release): Trace vr_busy and vscr_busy. (model_new_cycle): Update vr_busy and vscr_busy. (model_make_busy): Update vr_busy and vscr_busy. * registers.c (register_description): Add Altivec and e500 registers. * psim.c (psim_read_register, psim_read_register): Handle Altivec and e500 registers. * ppc-spr-table (SPEFSCR): Add VRSAVE and SPEFSCR registers. * configure.in (sim_filter): When *altivec* add "av". When *spe* or *simd* add e500. (sim_float): When *altivec* define WITH_ALTIVEC. When *spe* add WITH_E500. * configure: Re-generate. * e500.igen, altivec.igen: New files. * e500_expression.h, altivec_expression.h: New files. * idecode_expression.h: Update copyright. Include "e500_expression.h" and "altivec_expression.h". * e500_registers.h, altivec_registers.h: New files. * registers.h: Update copyright. Include "e500_registers.h" and "altivec_registers.h". (registers): Add Altivec and e500 specific registers. * Makefile.in (IDECODE_H): Add "idecode_e500.h" and "idecode_altivec.h". (REGISTERS_H): Add "e500_registers.h" and "altivec_registers.h". (tmp-igen): Add dependencies on altivec.igen and e500.igen .
2003-06-222003-06-21 Andrew Cagney <cagney@redhat.com>Andrew Cagney1-0/+1
* ppc-instructions: Add missing +8 line. Found by blofeldus at yahoo.com.
2003-06-202003-06-19 Andrew Cagney <cagney@redhat.com>Andrew Cagney1-1/+48
* ld-insn.h: Update copyright. (cache_fields): Define. (insn_table_fields): Add insn_field_6 and insn_field_7. (load_insn_table): Pass in the "cache_rules". * ld-insn.c: Update copyright. (load_insn_table): Add parameter "cache_rules". Handle "cache", "computed" and "scratch" fields. (main): Pass "cache_rules" to load_insn_table. * ld-cache.h: Update copyright. (append_cache_table): Declare. * ld-cache.c: Update copyright. (append_cache_table): New function. (load_cache_table): Call. * gen-model.c: Include "ld-cache.h". * gen-itable.c: Include "ld-cache.h". * igen.c: Move #include "ld-cache.h" to earlier. Update copyright. (main): Permit a NULL "cache_rules". Pass address of "cache_rules" to load_insn_table. * Makefile.in (tmp-ld-insn): Add "ld-cache.o". (tmp-igen): Do not include ppc-cache-rules. (gen-itable.o, gen-model.o): Add "ld-cache.h". * ppc-cache-rules: Delete file. * ppc-instructions: Add cache rules.
2002-03-23From 2001-12-09 Julien Ducourthial <jducourt@noos.fr>:Andrew Cagney1-7/+7
* ppc-instructions (lswx): Do the register control with the register count. Initialize the right register in the loop. (mtfsfi) : Correct prefix for the instruction.
2000-10-24 * ppc-instructions (lfsux): Correct XO field of lfsux instruction.Geoffrey Keating1-1/+1
2000-03-25* ppc-instructions (Disabled_Exponent_Underflow): IncrementGeoffrey Keating1-1/+1
the exponent when denormalizing.
1999-04-26import gdb-19990422 snapshotStan Shebs1-11/+5
1999-04-16Initial creation of sourceware repositorygdb-4_18-branchpointStan Shebs1-0/+4933
1999-04-16Initial creation of sourceware repositoryStan Shebs1-4857/+0
1997-01-27January 23rd mergeMichael Meissner1-91/+316
1996-07-23New simulator changes from AndrewMichael Meissner1-195/+221
1996-01-16Make {add to,subtract from} minus one; Make -t alu work betterMichael Meissner1-14/+49
1995-11-28Add determining when we do not have enough writeback slots; Do not do model ↵Michael Meissner1-54/+116
specific handling if not printing out the information
1995-11-25Make WITH_MODEL_ISSUE==0 not core dumpMichael Meissner1-13/+21
1995-11-25Sort instruction names; Add igen -R option; count # of CRs that mtcrf movedMichael Meissner1-197/+215
1995-11-24Fix warnings to everything can be compiled with -Wall; Redo model specific ↵Michael Meissner1-784/+297
changes once again to speed things up
1995-11-22Count each type of conditional branchMichael Meissner1-5/+55
1995-11-21Add floating point model specific support; Redo method model specific ↵Michael Meissner1-205/+917
support is done; Add remaining floating add/subtract-multiply
1995-11-20speed up search for free function unit slightly.Michael Meissner1-17/+80
1995-11-18Add scheduling support for M{F,T}CRMichael Meissner1-8/+72
1995-11-18More scheduling stuffMichael Meissner1-684/+1203
1995-11-17checkpoint ppc simulatorMichael Meissner1-682/+813
1995-11-16Delete old functional_unit support; Add --enable-sim-model-issue; Monitor ↵Michael Meissner1-11/+81
branch prediction success
1995-11-16fix bug in last checkinMichael Meissner1-1/+1
1995-11-16more functional unit changesMichael Meissner1-123/+821
1995-11-15More model specific changesMichael Meissner1-36/+233
1995-11-13Add model-functions supportMichael Meissner1-0/+3
1995-11-12Add support for setting model name and other thingsMichael Meissner1-0/+40
1995-11-08first stage in function unit support; add new switches & latest code from andrewMichael Meissner1-24/+24
1995-11-03Add 2 config flags that were missing; make data cache instructions be nopsMichael Meissner1-0/+9
1995-11-01Lots of changesMichael Meissner1-0/+2414
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