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2022-11-02sim: common: change sim_{fetch,store}_register helpers to use void* buffersMike Frysinger1-4/+4
When reading/writing arbitrary data to the system's memory, the unsigned char pointer type doesn't make that much sense. Switch it to void so we align a bit with standard C library read/write functions, and to avoid having to sprinkle casts everywhere.
2022-10-31sim: reg: constify store helperMike Frysinger1-3/+3
These functions only read from memory, so mark the pointer as const.
2022-01-06sim: mn10300: migrate to standard uintXX_t typesMike Frysinger1-3/+3
This old port setup its own uintXX types, but since we require C11 now, we can assume the standard uintXX_t types exist and use them.
2021-11-15sim: split program path out of argv vectorMike Frysinger1-5/+1
We use the program argv to both find the program to run (argv[0]) and to hold the arguments to the program. Most of the time this is fine, but if we want to let programs specify argv[0] independently (which is possible in standard *NIX programs), this double duty doesn't work. So let's split the path to the program to run out into a separate field by itself. This simplifies the various sim_open funcs too. By itself, this code is more of a logical cleanup than something that is super useful. But it will open up customization of argv[0] in a follow up commit. Split the changes to make it easier to review.
2021-06-18sim: split sim-signal.h include outMike Frysinger1-0/+1
The sim-basics.h is too big and includes too many things. This leads to some arch's sim-main.h having circular loop issues with defs, and makes it hard to separate out common objects from arch-specific defs. By splitting up sim-basics.h and killing off sim-main.h, it'll make it easier to separate out the two.
2021-06-17sim: overhaul & unify endian settings managementMike Frysinger1-0/+3
The m4 macro has 2 args: the "wire" settings (which represents the hardwired port behavior), and the default settings (which are used if nothing else is specified). If none are specified, the arch is expected to support both, and the value will be probed based on the user runtime options or the input program. Only two arches today set the default value (bpf & mips). We can probably let this go as it only shows up in one scenario: the sim is invoked, but with no inputs, and no user endian selection. This means bpf will not behave like the other arches: an error is shown and forces the user to make a choice. If an input program is used though, we'll still switch the default to that. This allows us to remove the WITH_DEFAULT_TARGET_BYTE_ORDER setting. For the ports that set a "wire" endian, move it to the runtime init of the respective sim_open calls. This allows us to change the WITH_TARGET_BYTE_ORDER to purely a user-selected configure setting if they want to force a specific endianness. With all the endian logic moved to runtime selection, we can move the configure call up to the common dir so we only process it once across all ports. The ppc arch was picking the wire endian based on the target used, but since we weren't doing that for other biendian arches, we can let this go too. We'll rely on the input selecting the endian, or make the user decide.
2021-05-29sim: mn10300: add SIGTRAP fallbackMike Frysinger1-0/+3
This is a bit of a hack, but it matches the hack we use in other places in the sim currently. This fixes building for e.g. Windows. The signal fallback logic needs a bit of love in general at some point across all sim code.
2021-05-16sim: switch config.h usage to defs.hMike Frysinger1-1/+3
The defs.h header will take care of including the various config.h headers. For now, it's just config.h, but we'll add more when we integrate gnulib in. This header should be used instead of config.h, and should be the first include in every .c file. We won't rely on the old behavior where we expected files to include the port's sim-main.h which then includes the common sim-basics.h which then includes config.h. We have a ton of code that includes things before sim-main.h, and it sometimes needs to be that way. Creating a dedicated header avoids the ordering mess and implicit inclusion that shows up otherwise.
2021-04-12sim: cgen: move cgen_cpu_max_extra_bytes logic into the common codeMike Frysinger1-1/+1
Every arch handles this the same way, so move it to the common code. This will also make unifying the sim_cpu structure easier.
2021-02-06sim: watchpoints: use common sim_pc_getMike Frysinger1-1/+0
Few arches implement STATE_WATCHPOINTS()->pc while all of them implement sim_pc_get. Lets switch the sim-watch core for monitoring pc events to the sim_pc_get API so this module works for all ports, and then we can delete this old back channel of snooping in the port's cpu state -- the code needs the pointer to the pc storage so that it can read out bytes and compare them to the watchrange. This also fixes the logic on multi-cpu sims by removing the limitation of only being able to watch CPU0's state.
2021-01-30sim: watchpoints: change sizeof_pc to sizeof(sim_cia)Mike Frysinger1-1/+0
Existing ports already have sizeof_pc set to the same size as sim_cia, so simply make that part of the core code. We already assume this in places by way of sim_pc_{get,set}, and this is how it's documented in the sim-base.h API. There is code to allow sims to pick different register word sizes from address sizes, but most ports use the defaults for both (32-bits), and the few that support multiple register sizes never change the address size (so address defaults to register). I can't think of any machine where the register hardware size would be larger than the address word size either. We have ABIs that behave that way (e.g. x32), but the hardware is still equivalent register sized.
2021-01-11sim: clean up C11 header includesMike Frysinger1-10/+0
Since we require C11 now, we can assume many headers exist, and clean up all of the conditional includes. It's not like any of this code actually accounted for the headers not existing, just whether we could include them. The strings.h cleanup is a little nuanced: it isn't in C11, but every use of it in the codebase will include strings.h only if string.h doesn't exist. Since we now assume the C11 string.h exists, we'll never include strings.h, so we can delete it.
2016-01-06sim: sim_{create_inferior,open,parse_args}: constify argv/env slightlyMike Frysinger1-3/+3
2016-01-03 Mike Frysinger <vapier@gentoo.org> * sim-options.c (sim_parse_args): Mark argv array const. * sim-options.h (sim_parse_args): Likewise.
2016-01-03sim: parse_args: display getopt error ourselvesMike Frysinger1-3/+1
Fix a long standing todo where we let getopt write directly to stderr when an invalid option is passed. Use the sim io funcs instead as they go through the filtered callbacks that gdb wants.
2015-12-30sim: arm/d10v/h8300/m68hc11/microblaze/mips/mn10300/moxie/sh/v850: convert ↵Mike Frysinger1-10/+9
to common sim_{fetch,store}_register
2015-11-22sim: mn10300: drop global callback handleMike Frysinger1-6/+1
It's used in one place and can easily be replaced by using the sim state.
2015-11-15sim: sim-close: unify sim_close logicMike Frysinger1-8/+0
Other than the nice advantage of all sims having to declare one fewer common function, this also fixes leakage in pretty much every sim. Many were not freeing any resources, and a few were inconsistent as to the ones they did. Now we have a single module that takes care of all the logic for us. Most of the non-cgen based ones could be deleted outright. The cgen ones required adding a callback to the arch-specific cleanup func. The few that still have close callbacks are to manage their internal state. We do not convert erc32, m32c, ppc, rl78, or rx as they do not use the common sim core.
2015-06-11sim: mn10300: delete unused memory codeMike Frysinger1-47/+8
Only one place used get_word/put_word, so inline the usage there. All the rest is dead code so trim it.
2015-06-11sim: mn10300: add missing static markingsMike Frysinger1-2/+2
2015-06-11sim: mn10300: delete unused exception/exited/debug stateMike Frysinger1-1/+0
The syscall path was the only code checking the custom exception state after recent cleanups. Once we change that to the common engine halt function, we can delete that state entirely. This also helps highlight some other dead code that we can cull.
2015-06-11sim: m68hc11/mn10300/v850: delete redundant INLINE definesMike Frysinger1-8/+0
The sim-inline.h header already takes care of this for us, so punt the local definitions.
2015-04-17sim: replace CIA_{GET,SET} with CPU_PC_{GET,SET}Mike Frysinger1-6/+6
The CIA_{GET,SET} macros serve the same function as CPU_PC_{GET,SET} except the latter adds a layer of indirection via the sim state. This lets models set up different functions at runtime and doesn't reach so directly into the arch-specific cpu state. It also doesn't make sense to have two sets of macros that do exactly the same thing, so lets standardize on the one that gets us more.
2015-04-13sim: mn10300: convert to sim-cpuMike Frysinger1-6/+26
Make cpu allocation fully dynamic so we can leverage the common sim-cpu and its APIs.
2015-03-24sim: m68hc11/mips/mn10300/v850: add basic sim_pc_getMike Frysinger1-0/+5
The previous profile change broke these sims that use sim-profile but not sim-cpu (due to missing model support). Add simple funcs until we can convert these over properly.
2012-06-17 * interp.c: Include config.h first. Do not include sysdep.h.Hans-Peter Nilsson1-1/+1
2012-02-16Update sim_fetch_register, sim_store_register for sh and mn10300.Kevin Buettner1-1/+1
Fix compile warnings for sh built on 64-bit hosts.
2011-07-05sim: start a unified sim_do_commandMike Frysinger1-17/+0
Since sim_do_command for many people simply calls sim_args_command, start a unified version of it. For people who handle their own options, they could switch to this by using sim_add_option_table instead. Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2011-01-11http://sourceware.org/ml/gdb-patches/2010-11/msg00112.htmlAndrew Burgess1-1/+1
gdb/ChangeLog * remote-sim.c (gdbsim_store_register): Update API to sim_store_register to check more error conditions. include/gdb/ChangeLog * remote-sim.h (sim_store_register): Update the API documentation for this function. sim/erc32/ChangeLog sim/h8300/ChangeLog sim/m32c/ChangeLog sim/mn10300/ChangeLog sim/ppc/ChangeLog sim/rx/ChangeLog sim/v850/ChangeLog * ???.c (sim_store_register): Update return value to match new API.
2004-06-262000-08-07 Graham Stott <grahams@cygnus.co.uk>Alexandre Oliva1-0/+569
* am33-2.igen (fmadd, fmsub, fmnadd, fmnsub): Correct typo. 2000-05-29 Alexandre Oliva <aoliva@cygnus.com> * interp.c (fpu_disabled_exception, fpu_unimp_exception, fpu_check_signal_exception): Take additional state arguments. Print exception type and call program_interrupt. Adjust callers. (fpu_rsqrt, fpu_cmp, fpu_add, fpu_sub, fpu_mul, fpu_div, fpu_fmadd, fpu_fmsub, fpu_fnmadd, fpu_fnmsub): Take additional arguments. * mn10300_sim.h (fpu_disabled_exception, fpu_unimp_exception, fpu_check_signal_exception): Adjust prototypes. (fpu_rsqrt, fpu_cmp, fpu_add, fpu_sub, fpu_mul, fpu_div, fpu_fmadd, fpu_fmsub, fpu_fnmadd, fpu_fnmsub): Likewise. * am33-2.igen: Adjust calls. 2000-05-19 Alexandre Oliva <aoliva@cygnus.com> * op_utils.c (cmp2fcc): Moved... * interp.c: ... here. 2000-05-18 Alexandre Oliva <aoliva@cygnus.com> * am33-2.igen: Use `unsigned32', `signed32', `unsigned64' or `signed64' where type width is relevant. 2000-05-15 Alexandre Oliva <aoliva@cygnus.com> * mn10300_sim.h: Include sim-fpu.h. (FD2FPU, FPU2FD): Enclose the FD argument in parentheses. (fpu_check_signal_exception): Declare. (struct fp_prec_t, fp_single_prec, fp_double_prec): Likewise. (FP_SINGLE, FP_DOUBLE): Shorthands for fp_*_prec. (fpu_rsqrt, fpu_cmp, fpu_add, fpu_sub, fpu_mul, fpu_div, fpu_fmadd, fpu_fmsub, fpu_fnmadd, fpu_fnmsub): Declare. * interp.c (fpu_disabled_exception): Document. (fpu_unimp_exception): Likewise. (fpu_check_signal_exception): Define. (reg2val_32, round_32, val2reg_32, fp_single_prec): Likewise. (reg2val_64, round_64, val2reg_64, fp_double_prec): Likewise. (REG2VAL, ROUND, VAL2REG): Define shorthands. (fpu_status_ok): Define. (fpu_rsqrt, fpu_cmp, fpu_add, fpu_sub, fpu_mul, fpu_div, fpu_fmadd, fpu_fmsub, fpu_fnmadd, fpu_fnmsub): Define. * am33-2.igen (frsqrt, fcmp, fadd, fsub, fmul, fdiv, fmadd, fmsub, fnmadd, fnmsub): Use new functions. 2000-04-27 Alexandre Oliva <aoliva@cygnus.com> * interp.c (sim_create_inferior): Set PSW bit to enable FP insns if architecture is AM33/2.0. * am33.igen: Include am33-2.igen. 2000-04-23 Alexandre Oliva <aoliva@cygnus.com> * mn10300.igen (movm, call, ret, retf): Check for am33_2 too. * am33.igen (movm): Likewise. 2000-04-19 Alexandre Oliva <aoliva@cygnus.com> * am33.igen: Added `*am33_2' to some instructions that were missing it. 2000-04-07 Alexandre Oliva <aoliva@cygnus.com> * am33-2.igen: New file. All insns implemented, but FP flags are only set for fcmp, exceptional conditions are not handled yet. * Makefile.in (IGEN_INSN): Added am33-2.igen. (tmp-igen): Added -M am33_2. * mn10300.igen, am33.igen: Added `*am33_2' to all insns. * gencode.c: Support FMT_D3. * mn10300_sim.h (dword): New type. (struct _state): Added fpregs. (REG_FPCR, FPCR): New define. All assorted bitmaps. (XS2FS, AS2FS, Xf2FD): New macros. (FS2FPU, FD2FPU, FPU2FS, FPU2FD): Likewise. (load_dword, store_dword): New functions or macros. (u642dw, dw2u64): New functions. (fpu_disabled_exception, fpu_unimp_exception): Declared. * interp.c (fpu_disabled_exception): Defined; no actual implementation. (fpu_unimp_exception): Likewise. * op_utils.c (cmp2fcc): New function.
2004-06-26* interp.c, mn10300_sim.h, op_utils.c: Convert function prototypesAlexandre Oliva1-54/+36
and definitions to ISO C.
2004-06-26* configure.in: Use common simulator always. Don't subst sim_genAlexandre Oliva1-856/+0
nor mn10300_common. * configure: Rebuilt. * Makefile.in (WITHOUT_COMMON_OBJS, WITHOUT_COMMON_INTERP_DEP, WITHOUT_COMMON_RUN_OBJS): Remove. (WITH_COMMON_OBJS): Rename to MN10300_OBJS. (WITH_COMMON_INTERP_DEP): Rename to MN10300_INTERP_DEP. (WITH_COMMON_RUN_OBJS): Rename to SIM_RUN_OBJS. (SIM_EXTRA_CFLAGS): Don't use @sim_gen@. * interp.c: Remove non-common bits. * mn10300_sim.h: Likewise.
2003-02-27Index: arm/ChangeLogAndrew Cagney1-4/+4
2003-02-27 Andrew Cagney <cagney@redhat.com> * wrapper.c (sim_create_inferior, sim_open): Rename _bfd to bfd. Index: common/ChangeLog 2003-02-27 Andrew Cagney <cagney@redhat.com> * sim-utils.h (sim_analyze_program, sim_load_file): Rename _bfd to bfd. * sim-hload.c (sim_load), sim-base.h (sim_state_base): Ditto. * nrun.c (main): Ditto. Index: d10v/ChangeLog 2003-02-27 Andrew Cagney <cagney@redhat.com> * interp.c (sim_open, sim_create_inferior): Rename _bfd to bfd. Index: erc32/ChangeLog 2003-02-27 Andrew Cagney <cagney@redhat.com> * interf.c (sim_open, sim_create_inferior): Rename _bfd to bfd. Index: h8300/ChangeLog 2003-02-27 Andrew Cagney <cagney@redhat.com> * compile.c (sim_open, sim_create_inferior): Rename _bfd to bfd. Index: h8500/ChangeLog 2003-02-27 Andrew Cagney <cagney@redhat.com> * compile.c (sim_open, sim_create_inferior): Rename _bfd to bfd. Index: i960/ChangeLog 2003-02-27 Andrew Cagney <cagney@redhat.com> * sim-if.c (sim_open, sim_create_inferior): Rename _bfd to bfd. Index: m32r/ChangeLog 2003-02-27 Andrew Cagney <cagney@redhat.com> * sim-if.c (sim_open, sim_create_inferior): Rename _bfd to bfd. Index: m68hc11/ChangeLog 2003-02-27 Andrew Cagney <cagney@redhat.com> * interp.c (sim_prepare_for_program, sim_open) (sim_create_inferior): Rename _bfd to bfd. Index: mcore/ChangeLog 2003-02-27 Andrew Cagney <cagney@redhat.com> * interp.c (sim_open, sim_create_inferior): Rename _bfd to bfd. Index: mips/ChangeLog 2003-02-27 Andrew Cagney <cagney@redhat.com> * interp.c (sim_open): (sim_create_inferior): Index: mn10200/ChangeLog 2003-02-27 Andrew Cagney <cagney@redhat.com> * interp.c (sim_open, sim_create_inferior): Rename _bfd to bfd. Index: mn10300/ChangeLog 2003-02-27 Andrew Cagney <cagney@redhat.com> * interp.c (sim_open, sim_create_inferior, sim_open) (sim_create_inferior): Rename _bfd to bfd. Index: ppc/ChangeLog 2003-02-27 Andrew Cagney <cagney@redhat.com> * sim_calls.c (sim_open, sim_create_inferior): Rename _bfd to bfd. Index: sh/ChangeLog 2003-02-27 Andrew Cagney <cagney@redhat.com> * interp.c (init_dsp, sim_open, sim_create_inferior): Rename _bfd to bfd. Index: v850/ChangeLog 2003-02-27 Andrew Cagney <cagney@redhat.com> * interp.c (sim_open, sim_create_inferior): Rename _bfd to bfd. Index: z8k/ChangeLog 2003-02-27 Andrew Cagney <cagney@redhat.com> * iface.c (sim_open, sim_create_inferior): Rename _bfd to bfd.
1999-07-19import gdb-1999-07-19 snapshotJason Molenda1-4/+4
1999-04-26import gdb-19990422 snapshotStan Shebs1-4/+24
1999-04-16Initial creation of sourceware repositorygdb-4_18-branchpointStan Shebs1-0/+1402
1999-04-16Initial creation of sourceware repositoryStan Shebs1-1402/+0
1998-12-30* eCos->devo merge; am30 sanitization tags removedFrank Ch. Eigler1-113/+254
1998-12-29 Frank Ch. Eigler <fche@cygnus.com> * Makefile.in (WITH_COMMON_OBJS): Build also dv-sockser.o. * interp.c (sim_open): Add stub mn103002 cache control memory regions. Set OPERATING_ENVIRONMENT on "stdeval1" board. (mn10300_core_signal): New function to intercept memory errors. (program_interrupt): New function to dispatch to exception vector (mn10300_exception_*): New functions to snapshot pre/post exception state. * sim-main.h (SIM_CORE_SIGNAL): Define hook - call mn10300_core_signal. (SIM_ENGINE_HALT_HOOK): Do nothing. (SIM_CPU_EXCEPTION*): Define hooks to call mn10300_cpu_exception*(). (_sim_cpu): Add exc_* fields to store register value snapshots. * dv-mn103ser.c (*): Support dv-sockser backend for UART I/O. Various endianness and warning fixes. * mn10300.igen (illegal): Call program_interrupt on error. (break): Call program_interrupt on breakpoint Several changes from <janczyn@cygnus.com> and <cagney@cygnus.com> merged in: * dv-mn103int.c (mn103int_ioctl): New function for NMI generation. (mn103int_finish): Install it as ioctl handler. * dv-mn103tim.c: Support timer 6 specially. Endianness fixes.
1998-06-19Fri Jun 19 11:59:26 1998 Joyce Janczyn <janczyn@cygnus.com>Joyce Janczyn1-1/+1
* interp.c (board): Rename am32 to stdeval1 as this is the name consistently used to refer to the mn1030002 board.
1998-06-18Thu June 18 14:37:14 1998 Joyce Janczyn <janczyn@cygnus.com>Joyce Janczyn1-1/+4
* interp.c (sim_open): Fix typo in address of EXTMD register (0x34000280, not 0x3400280).
1998-06-08 * interp.c: (mn10300_option_handler): New function parses argumentsJoyce Janczyn1-114/+156
using sim-options. start-sanitize-am30 * (board): Add --board option for specifying am32. * (sim_open): Create new timer and serial devices and control configuration of other am32 devices via board option. end-sanitize-am30
1998-03-27Add sanitize-am30 markers. Keep details of AM30 implementation ofAndrew Cagney1-24/+30
mn10300 out of the public eye. Do something with top-level cgen directory.
1998-03-25* interp.c (sim_open): Create second 1mb memory region at 0x40000000.Andrew Cagney1-150/+119
(sim_open): Create a device tree. (sim-hw.h): Include. (do_interrupt): Delete, needs to use dv-mn103cpu.c * dv-mn103int.c, dv-mn103cpu.c: New files.
1998-03-25Pacify GCC.Andrew Cagney1-3/+4
1998-03-24Add code to support building mn10300 simulator with the common simulatorJoyce Janczyn1-79/+398
framework.
1997-08-26Flush defunct sim_kill.Andrew Cagney1-7/+0
1997-08-25Add ABFD argument to sim_open call. Pass through to sim_config soAndrew Cagney1-3/+9
that image properties such as endianness can be checked. More strongly document the expected behavour of each of the sim_* interfaces. Add default endian argument to simulator config macro SIM_AC_OPTION_ENDIAN. Use in sim_config.
1997-05-22 * interp.c (sim_resume): Add missing case in big switchJeff Law1-0/+1
statement (for extb instruction).
1997-05-20 * interp.c: Replace all references to load_mem and store_memJeff Law1-85/+23
with references to load_byte, load_half, load_3_byte, load_word and store_byte, store_half, store_3_byte, store_word. (INLINE): Delete definition. (load_mem_big): Likewise. (max_mem): Make it global. (dispatch): Make this function inline. (load_mem, store_mem): Delete functions. * mn10300_sim.h (INLINE): Define. (RLW): Delete unused definition. (load_mem, store_mem): Delete declarations. (load_mem_big): New definition. (load_byte, load_half, load_3_byte, load_word): New functions. (store_byte, store_half, store_3_byte, store_word): New functions. * simops.c: Replace all references to load_mem and store_mem with references to load_byte, load_half, load_3_byte, load_word and store_byte, store_half, store_3_byte, store_word.
1997-05-19 * interp.c (dispatch): Make this an inline function.Jeff Law1-1/+1
* simops.c (syscall): Use callback->write regardless of what file descriptor we're writing too.
1997-05-18 * interp.c (load_mem_big): Remove function. It's now a macroJeff Law1-26/+24
defined elsewhere. (compare_simops): New function. (sim_open): Sort the Simops table before inserting entries into the hash table. * mn10300_sim.h: Remove unused #defines. (load_mem_big): Define. Another 20% so performance improvement for the mn10300 simulator.
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