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2003-02-27Index: arm/ChangeLogAndrew Cagney1-0/+5
2003-02-27 Andrew Cagney <cagney@redhat.com> * wrapper.c (sim_create_inferior, sim_open): Rename _bfd to bfd. Index: common/ChangeLog 2003-02-27 Andrew Cagney <cagney@redhat.com> * sim-utils.h (sim_analyze_program, sim_load_file): Rename _bfd to bfd. * sim-hload.c (sim_load), sim-base.h (sim_state_base): Ditto. * nrun.c (main): Ditto. Index: d10v/ChangeLog 2003-02-27 Andrew Cagney <cagney@redhat.com> * interp.c (sim_open, sim_create_inferior): Rename _bfd to bfd. Index: erc32/ChangeLog 2003-02-27 Andrew Cagney <cagney@redhat.com> * interf.c (sim_open, sim_create_inferior): Rename _bfd to bfd. Index: h8300/ChangeLog 2003-02-27 Andrew Cagney <cagney@redhat.com> * compile.c (sim_open, sim_create_inferior): Rename _bfd to bfd. Index: h8500/ChangeLog 2003-02-27 Andrew Cagney <cagney@redhat.com> * compile.c (sim_open, sim_create_inferior): Rename _bfd to bfd. Index: i960/ChangeLog 2003-02-27 Andrew Cagney <cagney@redhat.com> * sim-if.c (sim_open, sim_create_inferior): Rename _bfd to bfd. Index: m32r/ChangeLog 2003-02-27 Andrew Cagney <cagney@redhat.com> * sim-if.c (sim_open, sim_create_inferior): Rename _bfd to bfd. Index: m68hc11/ChangeLog 2003-02-27 Andrew Cagney <cagney@redhat.com> * interp.c (sim_prepare_for_program, sim_open) (sim_create_inferior): Rename _bfd to bfd. Index: mcore/ChangeLog 2003-02-27 Andrew Cagney <cagney@redhat.com> * interp.c (sim_open, sim_create_inferior): Rename _bfd to bfd. Index: mips/ChangeLog 2003-02-27 Andrew Cagney <cagney@redhat.com> * interp.c (sim_open): (sim_create_inferior): Index: mn10200/ChangeLog 2003-02-27 Andrew Cagney <cagney@redhat.com> * interp.c (sim_open, sim_create_inferior): Rename _bfd to bfd. Index: mn10300/ChangeLog 2003-02-27 Andrew Cagney <cagney@redhat.com> * interp.c (sim_open, sim_create_inferior, sim_open) (sim_create_inferior): Rename _bfd to bfd. Index: ppc/ChangeLog 2003-02-27 Andrew Cagney <cagney@redhat.com> * sim_calls.c (sim_open, sim_create_inferior): Rename _bfd to bfd. Index: sh/ChangeLog 2003-02-27 Andrew Cagney <cagney@redhat.com> * interp.c (init_dsp, sim_open, sim_create_inferior): Rename _bfd to bfd. Index: v850/ChangeLog 2003-02-27 Andrew Cagney <cagney@redhat.com> * interp.c (sim_open, sim_create_inferior): Rename _bfd to bfd. Index: z8k/ChangeLog 2003-02-27 Andrew Cagney <cagney@redhat.com> * iface.c (sim_open, sim_create_inferior): Rename _bfd to bfd.
2003-02-26Index: common/ChangeLogAndrew Cagney1-0/+4
2003-02-26 Andrew Cagney <cagney@redhat.com> * sim-engine.h (sim_engine_abort): Add noreturn attribute. (sim_engine_vabort): Ditto. (sim_engine_halt, sim_engine_restart): Ditto. Index: mn10300/ChangeLog 2003-02-26 Andrew Cagney <cagney@redhat.com> * am33.igen: Call sim_engine_abort instead of abort.
2003-02-262003-02-26 David Carlton <carlton@math.stanford.edu>David Carlton1-0/+7
* dv-mn103tim.c (read_special_timer6_reg): Add break after empty default: label. (write_special_timer6_reg): Ditto. Update copyright.
2002-11-282002-11-28 Andrew Cagney <cagney@redhat.com>Andrew Cagney1-0/+5
* sim-main.h: Only include "idecode.h" once. * Makefile.in (SIM_EXTRA_DEPS): Define.
2002-06-16Import current --enable-gdb-build-warnings.Andrew Cagney1-0/+4
2002-06-09Move include/callback.h and include/remote-sim.h to include/gdb/.Andrew Cagney1-0/+6
Update accordingly.
2001-05-07*** empty log message ***Jim Blandy1-0/+4
2001-04-26* Makefile.in (idecode.o, op_utils.o, semantics.o, simops.o):Alexandre Oliva1-0/+5
Depend on targ-vals.h.
2001-04-15* Makefile.in (simops.o): Add simops.h to dependency list.J.T. Conklin1-0/+4
2000-08-09* am33.igen: Warning clean-up.Alexandre Oliva1-0/+9
(movm): Initialize PC and mask. (mov, movbu, movhu): Set srcreg2 from RI0. (bsch): Initialize c. (sat16_cmp): Actually do the comparison. (mov_llt): Do not overwrite dstreg with uninitialized variable.
2000-05-24Change profiling so that it is enabled by default. Re-generate everything.Andrew Cagney1-0/+4
2000-05-22* am33.igen: Fix leading comments of SP-relative offset insns thatAlexandre Oliva1-0/+5
referred to other registers. Make their offsets unsigned.
2000-05-18* mn10300_sim.h (genericAdd, genericSub, genericCmp, genericOr,Alexandre Oliva1-0/+8
genericXor, genericBtst): Use `unsigned32'. * op_utils.c: Likewise. * mn10300.igen, am33.igen: Use `unsigned32', `signed32', `unsigned64' or `signed64' where type width is relevant.
2000-04-25* am33.igen (inc4 Rn): Use genericAdd so as to modify flags.Alexandre Oliva1-0/+4
2000-04-09* am33.igen: Make SP-relative offsets unsigned. Add `*am33' forAlexandre Oliva1-0/+5
some instructions that were missing it.
2000-03-03* build fixFrank Ch. Eigler1-0/+4
2000-03-03 Alexandre Oliva <oliva@lsd.ic.unicamp.br> * Makefile.in (IGEN_INSN): Added am33.igen.
1999-12-07import gdb-1999-12-06 snapshotJason Molenda1-0/+74
1999-09-09import gdb-1999-09-08 snapshotStan Shebs1-0/+4
1999-07-19import gdb-1999-07-19 snapshotJason Molenda1-0/+4
1999-05-11import gdb-1999-05-10Stan Shebs1-0/+4
1999-04-26import gdb-19990422 snapshotStan Shebs1-0/+25
1999-04-16Initial creation of sourceware repositorygdb-4_18-branchpointStan Shebs1-0/+815
1999-04-16Initial creation of sourceware repositoryStan Shebs1-883/+0
1998-08-26Regress yesterday's change to jmp instn implementation in mn10300.igen.Joyce Janczyn1-5/+0
1998-08-26Regress yesterday's change to jmp instruction -- it has deceiving syntax.Joyce Janczyn1-0/+5
Also tidy up some code to match documentation and fix div, divu by 0.
1998-08-25* mn10300.igen (OP_F0F4): Need to load contents of register AN0Joyce Janczyn1-0/+5
for jmp.
1998-08-24* sim-main.h (SIM_HANDLES_LMA): Define SIM_HANDLES_LMA.Joyce Janczyn1-0/+14
1998-07-27 * am33.igen: Detect cases where two operands must not match inJeff Law1-0/+7
non-DSP instructions.
1998-07-24Fri Jul 24 18:15:21 1998 Joyce Janczyn <janczyn@cygnus.com>Joyce Janczyn1-0/+10
* op_utils.c (do_syscall): Rewrite to use common/syscall.c. (syscall_read_mem, syscall_write_mem): New functions for syscall callbacks. * mn10300_sim.h: Add prototypes for syscall_read_mem and syscall_write_mem. * mn10300.igen: Change C++ style comments to C style comments. Check for divide by zero in div and divu ops.
1998-07-24 * am33.igen (translate_xreg): New function. Use it as needed.Jeff Law1-0/+4
1998-07-23 * am33.igen: Add some missing instructions.Jeff Law1-0/+2
Missed a few last week... Grrr.
1998-07-23 * am33.igen: Autoincrement loads/store fixes.Jeff Law1-0/+6
1998-07-21 * am33.igen: Add most am33 DSP instructions.Jeff Law1-0/+10
1998-07-09 * am33.igen: Fix Z bit for remaining addc/subc instructions.Jeff Law1-0/+6
Do not sign extend immediate for mov imm,XRn. More random mul, mac & div fixes. Remove some unused variables. Sign extend 24bit displacement in memory addresses. Whee, more fixes.
1998-07-09 * mn10300.igen: Fix Z bit for addc and subc instructions.Jeff Law1-1/+11
Minor fixes in multiply/divide patterns. start-sanitize-am33 * am33.igen: Fix Z bit for addc Rm,Rn and subc Rm,Rn. Various fixes to 2 register multiply, divide and mac instructions. Set Z,N correctly for sat16. Sign extend 24 bit immediate for add, and sub instructions. * am33.igen: Add remaining non-DSP instructions. end-sanitize-am33
1998-07-09 * am33.igen: Add remaining non-DSP instructions.Jeff Law1-0/+4
Lots of work still remains. PSW handing is probably broken badly and the mul/mac classes of instructions are probably not handled correctly.
1998-07-09 * am33.igen (translate_rreg): New function. Use it as appropriate.Jeff Law1-0/+2
1998-07-08 * am33.igen: More am33 instructions. Fix "div".Jeff Law1-0/+4
1998-07-06 * mn10300.igen: Add am33 support.Jeff Law1-0/+2
1998-07-06 * Makefile.in: Use multi-sim to support both a mn10300 and am33Jeff Law1-0/+3
simulator.
1998-07-06 * am33.igen: Add many more am33 instructions.Jeff Law1-0/+6
1998-07-01 * am33.igen: New file with some am33 support.Jeff Law1-0/+2
Checking in work-to-date.
1998-07-01 * mn10300_sim.h (FETCH24): Define.Jeff Law1-0/+7
* mn10300_sim.h: Add defines for some registers found on the AM33.
1998-06-30 * mn10300_sim.h: Include bfd.hJeff Law1-0/+8
(struct state): Add more room for processor specific registers. start-sanitize-am33 (REG_E0): Define. end-sanitize-am33
1998-06-25Thu Jun 25 10:12:03 1998 Joyce Janczyn <janczyn@cygnus.com>Joyce Janczyn1-0/+12
* dv-mn103tim.c: Include sim-assert.h * dv-mn103ser.c (do_polling_event): Check for incoming data on serial line and schedule next polling event. (read_status_reg): schedule events to check for incoming data on serial line and issue interrupt if necessary.
1998-06-19Fri Jun 19 11:59:26 1998 Joyce Janczyn <janczyn@cygnus.com>Joyce Janczyn1-0/+5
* interp.c (board): Rename am32 to stdeval1 as this is the name consistently used to refer to the mn1030002 board.
1998-06-18Thu June 18 14:37:14 1998 Joyce Janczyn <janczyn@cygnus.com>Joyce Janczyn1-2/+15
* interp.c (sim_open): Fix typo in address of EXTMD register (0x34000280, not 0x3400280).
1998-06-16Tue June 16 09:36:21 1998 Joyce Janczyn <janczyn@cygnus.com>Joyce Janczyn1-0/+4
* dv-mn103int.c (mn103int_finish): Regular interrupts (not NMI or reset) are not enabled on reset.
1998-06-14Updates to dv-mn103iop.c, dv-mn103ser.c and inter.cJoyce Janczyn1-0/+5
1998-06-12Fri June 12 16:24:00 1998 Joyce Janczyn <janczyn@cygnus.com>Joyce Janczyn1-0/+6
* dv-mn103iop.c: New file for handling am32 io ports. * configure.in: Add mn103iop to hw_device list. * configure: Re-generate. * interp.c (sim_open): Create io port device.
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