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AgeCommit message (Expand)AuthorFilesLines
1997-11-05Add option --enable-sim-igen to mips configuration. Allows user toAndrew Cagney2-17/+50
1997-11-05Rewrite the MIPS simulator's memory model so that it uses the genericAndrew Cagney5-544/+225
1997-11-05Delete -l and -n options, didn't do anything.Andrew Cagney3-51/+28
1997-11-05Rewrite sim_monitor (implements read, write, open, et.al. systemAndrew Cagney3-323/+249
1997-11-04Correct r5900 sanitization.Gavin Romig-Koch2-1/+3
1997-10-29 * gencode.c: Add tx49 configury and insns.Gavin Romig-Koch5-15/+97
1997-10-29common/sim-bits.h: Document ROTn macro.Andrew Cagney6-22/+720
1997-10-28Add support for 16 byte quantities to sim-endian macro H2T.Andrew Cagney2-26/+30
1997-10-27Separate r5900 specifoc and mips16 instructions.Andrew Cagney9-5179/+2770
1997-10-27Add mips64vr5400 to configuration listAndrew Cagney6-38/+636
1997-10-25 * sim/mips/gencode.c (build_instruction): Follow sim_write's lead in usingGavin Romig-Koch2-1/+7
1997-10-24Add basic igen configuration to autoconf. Disable.Andrew Cagney4-18/+244
1997-10-24Add function to fetch 32bit instructionsAndrew Cagney4-119/+154
1997-10-24Checkpoint IGEN version of mips simAndrew Cagney1-152/+157
1997-10-21Use SIM*_OVERFLOW_RESULT defined in sim-alu.hAndrew Cagney2-2/+7
1997-10-21Output pc profile statistics once gathered.Andrew Cagney2-9/+5
1997-10-21Delete profile support from MIPS simulator, use sim/common/sim-profileAndrew Cagney4-225/+19
1997-10-20Make mips registers of type unsigned_word.Andrew Cagney3-3/+14
1997-10-16Move register definitions and macros out of interp.c and into sim-main.hAndrew Cagney4-274/+362
1997-10-16Checkpoint IGEN version of MIPS simulator.Andrew Cagney1-248/+218
1997-10-16Rename generated file engine.c to oengine.c.Andrew Cagney3-6/+13
1997-10-16* gencode.c (build_instruction): Use FPR_STATE not fpr_state.Andrew Cagney2-6/+10
1997-10-16* gencode.c (build_instruction): For "FPSQRT", output correct numberAndrew Cagney2-1/+8
1997-10-14Checkpoint IGEN version of MIPS simulator.Andrew Cagney1-1239/+1196
1997-10-14Move global MIPS simulator variables into sim_cpu struct.Andrew Cagney4-330/+369
1997-10-14o Add support for configuring wordsize, fp hardware and targetAndrew Cagney8-543/+822
1997-10-09Snap. Gets through igen's checks.Andrew Cagney1-322/+104
1997-10-08MIPS/IGEN checkpoint - doesn't build.Andrew Cagney3-0/+10004
1997-10-07Checkpoint IGEN input file for MIPS simulator.Andrew Cagney1-0/+2
1997-09-30Add access to hi part of r5900 128 bit registers.Andrew Cagney1-0/+13
1997-09-29 * configure: Regenerated.Bob Manson1-0/+4
1997-09-26 * interp.c: Allow Debug, DEPC, and EPC registers to be examined in GDB.Mark Alexander2-7/+108
1997-09-25Add/use SIM_AC_OPTION_BITSIZE.Andrew Cagney1-10/+34
1997-09-25Allow gencode.c to generate input to the igen generator.Andrew Cagney2-201/+489
1997-09-25Pacify GCC -WallAndrew Cagney1-0/+5
1997-09-23vr5900-r5900.Jeff Law1-1/+1
1997-09-23Remove need to update <targ>/Makefile.in when adding optional optionsAndrew Cagney3-69/+160
1997-09-22Add memory alignment config option.Andrew Cagney3-44/+106
1997-09-22Simplify logic behind the generic configuration option --enable-sim-alignment.Andrew Cagney1-0/+4
1997-09-22Add support for --enable-sim-alignment to simulator common aclocal.m4Andrew Cagney1-0/+21
1997-09-20Add handling for 3900's SDBBP, DERET, and RFE insns.Gavin Romig-Koch2-7/+15
1997-09-19 * gencode.c: Add r3900 (tx39).Gavin Romig-Koch2-21/+40
1997-09-16 * sim/mips/gencode.c (build_instruction): Don't need to subtract 4 forGavin Romig-Koch2-1/+7
1997-09-16 * sim/mips/interp.c: Correct some HASFPU problems.Gavin Romig-Koch2-5/+19
1997-09-15Update to reflect change to sim/common/aclocal.m4 (allow sim/commonAndrew Cagney2-17/+24
1997-09-12Short form of sample-size option had wrong value.Andrew Cagney2-1/+6
1997-09-10mips/sim_info was just returning?????Andrew Cagney2-2/+4
1997-09-10Support tx19 sanitation.Gavin Romig-Koch1-0/+30
1997-09-09Better word error messages.Andrew Cagney2-2/+7
1997-09-09Remove GCC specific `0x...LL', replace with SIGNED64 (0x...).Andrew Cagney2-14/+17