aboutsummaryrefslogtreecommitdiff
path: root/sim/mips/sim-main.h
AgeCommit message (Collapse)AuthorFilesLines
2007-08-24 Switch the license of all files explicitly copyright the FSFJoel Brobecker1-5/+4
to GPLv3.
2007-01-09Copyright updates for 2007.Daniel Jacobowitz1-1/+1
2006-08-29 * configure.ac (mipsisa32r2*-*-*, mipsisa32*-*-*): Add smartmips toThiemo Seufer1-0/+1
sim_igen_machine. * configure: Regenerate. * mips.igen (model): Add smartmips. (MADDU): Increment ACX if carry. (do_mult): Clear ACX. (ROR,RORV): Add smartmips. (include): Include smartmips.igen. * sim-main.h (ACX): Set to REGISTERS[89]. * smartmips.igen: New file.
2005-12-14* Makefile.in (SIM_OBJS): Add dsp.o.Chao-ying Fu1-1/+49
(dsp.o): New dependency. (IGEN_INCLUDE): Add dsp.igen. * configure.ac (mipsisa32r2*-*-*, mipsisa32*-*-*, mipsisa64r2*-*-*, mipsisa64*-*-*): Add dsp to sim_igen_machine. * configure: Regenerate. * mips.igen: Add dsp model and include dsp.igen. (MFHI, MFLO, MTHI, MTLO): Remove mips32, mips32r2, mips64, mips64r2, because these instructions are extended in DSP ASE. * sim-main.h (LAST_EMBED_REGNUM): Change from 89 to 96 because of adding 6 DSP accumulator registers and 1 DSP control register. (AC0LOIDX, AC0HIIDX, AC1LOIDX, AC1HIIDX, AC2LOIDX, AC2HIIDX, AC3LOIDX, AC3HIIDX, DSPLO, DSPHI, DSPCRIDX, DSPCR, DSPCR_POS_SHIFT, DSPCR_POS_MASK, DSPCR_POS_SMASK, DSPCR_SCOUNT_SHIFT, DSPCR_SCOUNT_MASK, DSPCR_SCOUNT_SMASK, DSPCR_CARRY_SHIFT, DSPCR_CARRY_MASK, DSPCR_CARRY_SMASK, DSPCR_CARRY, DSPCR_EFI_SHIFT, DSPCR_EFI_MASK, DSPCR_EFI_SMASK, DSPCR_EFI, DSPCR_OUFLAG_SHIFT, DSPCR_OUFLAG_MASK, DSPCR_OUFLAG_SMASK, DSPCR_OUFLAG4, DSPCR_OUFLAG5, DSPCR_OUFLAG6, DSPCR_OUFLAG7, DSPCR_CCOND_SHIFT, DSPCR_CCOND_MASK, DSPCR_CCOND_SMASK): New define. (DSPLO_REGNUM, DSPHI_REGNUM): New array for DSP accumulators. * dsp.c, dsp.igen: New files for MIPS DSP ASE.
2004-05-122004-05-11 Maciej W. Rozycki <macro@ds2.pg.gda.pl>Chris Demetriou1-1/+1
* mips/interp.c (decode_coproc): Sign-extend the address retrieved from COP0_BADVADDR. * mips/sim-main.h (COP0_BADVADDR): Remove a cast.
2004-03-29 * sim-main.h (MIPS_MACH_HAS_MT_HILO_HAZARD)Richard Sandiford1-0/+12
(MIPS_MACH_HAS_MULT_HILO_HAZARD, MIPS_MACH_HAS_DIV_HILO_HAZARD): New. * mips.igen (check_mt_hilo, check_mult_hilo, check_div_hilo): Provide separate implementations for mipsIV and mipsV. Use new macros to determine whether the restrictions apply.
2003-01-052003-01-04 Richard Sandiford <rsandifo@redhat.com>Chris Demetriou1-2/+8
Andrew Cagney <ac131313@redhat.com> Gavin Romig-Koch <gavin@redhat.com> Graydon Hoare <graydon@redhat.com> Aldy Hernandez <aldyh@redhat.com> Dave Brolley <brolley@redhat.com> Chris Demetriou <cgd@broadcom.com> * configure.in (mips64vr*): Define TARGET_ENABLE_FR to 1. (sim_mach_default): New variable. (mips64vr-*-*, mips64vrel-*-*): New configurations. Add a new simulator generator, MULTI. * configure: Regenerate. * Makefile.in (SIM_MULTI_OBJ, SIM_EXTRA_DISTCLEAN): New variables. (multi-run.o): New dependency. (SIM_MULTI_ALL, SIM_MULTI_IGEN_CONFIGS): New variables. (tmp-mach-multi, tmp-itable-multi, tmp-run-multi): New rules. (tmp-multi): Combine them. (BUILT_SRC_FROM_MULTI): New variable. Depend on tmp-multi. (clean-extra): Remove sources in BUILT_SRC_FROM_MULTI. (distclean-extra): New rule. * sim-main.h: Include bfd.h. (MIPS_MACH): New macro. * mips.igen (vr4120, vr5400, vr5500): New models. (clo, clz, dclo, dclz, madd, maddu, msub, msub, mul): Add *vr5500. * vr.igen: Replace with new version.
2002-12-312002-12-31 Chris Demetriou <cgd@broadcom.com>Chris Demetriou1-4/+0
* sim-main.h (check_branch_bug, mark_branch_bug): Remove. * mips.igen: Remove all invocations of check_branch_bug and mark_branch_bug.
2002-06-142002-06-14 Chris Demetriou <cgd@broadcom.com>Chris Demetriou1-0/+21
Ed Satterthwaite <ehs@broadcom.com> * mips3d.igen: New file which contains MIPS-3D ASE instructions. * Makefile.in (IGEN_INCLUDE): Add mips3d.igen. * mips.igen: Include mips3d.igen. (mips3d): New model name for MIPS-3D ASE instructions. (CVT.W.fmt): Don't use this instruction for word (source) format instructions. * cp1.c (fp_binary_r, fp_add_r, fp_mul_r, fpu_inv1, fpu_inv1_32) (fpu_inv1_64, fp_recip1, fp_recip2, fpu_inv_sqrt1, fpu_inv_sqrt1_32) (fpu_inv_sqrt1_64, fp_rsqrt1, fp_rsqrt2): New functions. (NR_FRAC_GUARD, IMPLICIT_1): New macros. * sim-main.h (fmt_pw, CompareAbs, AddR, MultiplyR, Recip1, Recip2) (RSquareRoot1, RSquareRoot2): New macros. (fp_add_r, fp_mul_r, fp_recip1, fp_recip2, fp_rsqrt1) (fp_rsqrt2): New functions. * configure.in: Add MIPS-3D support to mipsisa64 simulator. * configure: Regenerate.
2002-06-142002-06-13 Chris Demetriou <cgd@broadcom.com>Chris Demetriou1-0/+10
* cp1.c (FP_PS_upper, FP_PS_lower, FP_PS_cat, FPQNaN_PS): New macros. (value_fpr, store_fpr, fp_cmp, fp_unary, fp_binary, fp_mac) (fp_inv_sqrt, fpu_format_name): Add paired-single support. (convert): Note that this function is not used for paired-single format conversions. (ps_lower, ps_upper, pack_ps, convert_ps): New functions. * mips.igen (FMT, MOVtf.fmt): Add paired-single support. (check_fmt_p): Enable paired-single support. (ALNV.PS, CVT.PS.S, CVT.S.PL, CVT.S.PU, PLL.PS, PLU.PS, PUL.PS) (PUU.PS): New instructions. (CVT.S.fmt): Don't use this instruction for paired-single format destinations. * sim-main.h (FP_formats): New value 'fmt_ps.' (ps_lower, ps_upper, pack_ps, convert_ps): New prototypes. (PSLower, PSUpper, PackPS, ConvertPS): New macros.
2002-06-082002-06-07 Chris Demetriou <cgd@broadcom.com>Chris Demetriou1-0/+14
Ed Satterthwaite <ehs@broadcom.com> * cp1.c (inner_mac, fp_mac, inner_rsqrt, fp_inv_sqrt) (fp_rsqrt, fp_madd, fp_msub, fp_nmadd, fp_nmsub): New functions. * sim-main.h (fp_rsqrt, fp_madd, fp_msub, fp_nmadd) (fp_nmsub): New prototypes. (RSquareRoot, MultiplyAdd, MultiplySub, NegMultiplyAdd) (NegMultiplySub): New defines. * mips.igen (RSQRT.fmt): Use RSquareRoot(). (MADD.D, MADD.S): Replace with... (MADD.fmt): New instruction. (MSUB.D, MSUB.S): Replace with... (MSUB.fmt): New instruction. (NMADD.D, NMADD.S): Replace with... (NMADD.fmt): New instruction. (NMSUB.D, MSUB.S): Replace with... (NMSUB.fmt): New instruction.
2002-06-072002-06-06 Chris Demetriou <cgd@broadcom.com>Chris Demetriou1-44/+12
Ed Satterthwaite <ehs@broadcom.com> * cp1.h: New file. * sim-main.h: Include cp1.h. (SETFCC, GETFCC, IR, UF, OF, DX, IO, UO, FP_FLAGS, FP_ENABLE) (FP_CAUSE, GETFS, FP_RM_NEAREST, FP_RM_TOZERO, FP_RM_TOPINF) (FP_RM_TOMINF, GETRM): Remove. Moved to cp1.h. (FP_FS, FP_MASK_RM, FP_SH_RM, Nan, Less, Equal): Remove. (value_fcr, store_fcr, test_fcsr, fp_cmp): New prototypes. (ValueFCR, StoreFCR, TestFCSR, Compare): New macros. * cp1.c: Don't include sim-fpu.h; already included by sim-main.h. Clean up formatting of some comments. (NaN, Equal, Less): Remove. (test_fcsr, value_fcr, store_fcr, update_fcsr, fp_test) (fp_cmp): New functions. * mips.igen (do_c_cond_fmt): Remove. (C.cond.fmta, C.cond.fmtb): Replace uses of do_c_cond_fmt_a with Compare. Add result tracing. (CxC1): Remove, replace with... (CFC1a, CFC1b, CFC1c, CTC1a, CTC1b, CTC1c): New instructions. (DMxC1): Remove, replace with... (DMFC1a, DMFC1b, DMTC1a, DMTC1b): New instructions. (MxC1): Remove, replace with... (MFC1a, MFC1b, MTC1a, MTC1b): New instructions.
2002-06-042002-06-04 Chris Demetriou <cgd@broadcom.com>Chris Demetriou1-13/+15
* sim-main.h (FGRIDX): Remove, replace all uses with... (FGR_BASE): New macro. (FP0_REGNUM, FCRCS_REGNUM, FCRIR_REGNUM): New macros. (_sim_cpu): Move 'fgr' member to be right before 'fpr_state' member. (NR_FGR, FGR): Likewise. * interp.c: Replace all uses of FGRIDX with FGR_BASE. * mips.igen: Likewise.
2002-06-042002-06-04 Chris Demetriou <cgd@broadcom.com>Chris Demetriou1-9/+16
Ed Satterthwaite <ehs@broadcom.com> * cp1.c (Infinity): Remove. * sim-main.h (Infinity): Likewise. * cp1.c (fp_unary, fp_binary): New functions. (fp_abs, fp_neg, fp_add, fp_sub, fp_mul, fp_div, fp_recip) (fp_sqrt): New functions, implemented in terms of the above. (AbsoluteValue, Negate, Add, Sub, Multiply, Divide) (Recip, SquareRoot): Remove (replaced by functions above). * sim-main.h (fp_abs, fp_neg, fp_add, fp_sub, fp_mul, fp_div) (fp_recip, fp_sqrt): New prototypes. (AbsoluteValue, Negate, Add, Sub, Multiply, Divide) (Recip, SquareRoot): Replace prototypes with #defines which invoke the functions above.
2002-06-042002-06-03 Chris Demetriou <cgd@broadcom.com>Chris Demetriou1-22/+24
* sim-main.h (Nan, Infinity, Less, Equal, AbsoluteValue, Negate) (Add, Sub, Multiply, Divide, Recip, SquareRoot): Move lower in file, remove PARAMS from prototypes. (value_fpr, store_fpr, convert): Likewise. Use SIM_STATE to provide simulator state arguments. (ValueFPR, StoreFPR, Convert): Move lower in file. Use SIM_ARGS to pass simulator state arguments. * cp1.c (SD): Redefine as CPU_STATE(cpu). (store_fpr, convert): Remove 'sd' argument. (value_fpr): Likewise. Convert to use 'SD' instead.
2002-06-042002-06-03 Chris Demetriou <cgd@broadcom.com>Chris Demetriou1-2/+0
* cp1.c (Min, Max): Remove #if 0'd functions. * sim-main.h (Min, Max): Remove.
2002-06-032002-06-03 Chris Demetriou <cgd@broadcom.com>Chris Demetriou1-1/+8
Ed Satterthwaite <ehs@broadcom.com> * configure.in (mipsisa64sb1*-*-*): New target for supporting Broadcom SiByte SB-1 processor configurations. * configure: Regenerate. * sb1.igen: New file. * mips.igen: Include sb1.igen. (sb1): New model. * Makefile.in (IGEN_INCLUDE): Add sb1.igen. * mdmx.igen: Add "sb1" model to all appropriate functions and instructions. * mdmx.c (AbsDiffOB, AvgOB, AccAbsDiffOB): New functions. (ob_func, ob_acc): Reference the above. (qh_acc): Adjust to keep the same size as ob_acc. * sim-main.h (status_SBX, MX_VECT_ABSD, MX_VECT_AVG, MX_AbsDiff) (MX_Avg, MX_VECT_ABSDA, MX_AbsDiffC): New macros.
2002-06-022002-06-02 Chris Demetriou <cgd@broadcom.com>Chris Demetriou1-0/+124
Ed Satterthwaite <ehs@broadcom.com> * mips.igen (mdmx): New (pseudo-)model. * mdmx.c, mdmx.igen: New files. * Makefile.in (SIM_OBJS): Add mdmx.o. * sim-main.h (MDMX_accumulator, MX_fmtsel, signed24, signed48): New typedefs. (ACC, MX_Add, MX_AddA, MX_AddL, MX_And, MX_C_EQ, MX_C_LT, MX_Comp) (MX_FMT_OB, MX_FMT_QH, MX_Max, MX_Min, MX_Msgn, MX_Mul, MX_MulA) (MX_MulL, MX_MulS, MX_MulSL, MX_Nor, MX_Or, MX_Pick, MX_RAC) (MX_RAC_H, MX_RAC_L, MX_RAC_M, MX_RNAS, MX_RNAU, MX_RND_AS) (MX_RND_AU, MX_RND_ES, MX_RND_EU, MX_RND_ZS, MX_RND_ZU, MX_RNES) (MX_RNEU, MX_RZS, MX_RZU, MX_SHFL, MX_ShiftLeftLogical) (MX_ShiftRightArith, MX_ShiftRightLogical, MX_Sub, MX_SubA, MX_SubL) (MX_VECT_ADD, MX_VECT_ADDA, MX_VECT_ADDL, MX_VECT_AND) (MX_VECT_MAX, MX_VECT_MIN, MX_VECT_MSGN, MX_VECT_MUL, MX_VECT_MULA) (MX_VECT_MULL, MX_VECT_MULS, MX_VECT_MULSL, MX_VECT_NOR) (MX_VECT_OR, MX_VECT_SLL, MX_VECT_SRA, MX_VECT_SRL, MX_VECT_SUB) (MX_VECT_SUBA, MX_VECT_SUBL, MX_VECT_XOR, MX_WACH, MX_WACL, MX_Xor) (SIM_ARGS, SIM_STATE, UnpredictableResult, fmt_mdmx, ob_fmtsel) (qh_fmtsel): New macros. (_sim_cpu): New member "acc". (mdmx_acc_op, mdmx_cc_op, mdmx_cpr_op, mdmx_pick_op, mdmx_rac_op) (mdmx_round_op, mdmx_shuffle, mdmx_wach, mdmx_wacl): New functions.
2002-05-01[ common/ChangeLog ]Chris Demetriou1-1/+1
2002-05-01 Chris Demetriou <cgd@broadcom.com> * callback.c: Use 'deprecated' rather than 'depreciated.' [ igen/ChangeLog ] 2002-05-01 Chris Demetriou <cgd@broadcom.com> * igen.c: Use 'deprecated' rather than 'depreciated.' [ mips/ChangeLog ] 2002-05-01 Chris Demetriou <cgd@broadcom.com> * interp.c: Use 'deprecated' rather than 'depreciated.' * sim-main.h: Likewise.
2002-05-012002-05-01 Chris Demetriou <cgd@broadcom.com>Chris Demetriou1-2/+3
* cp1.c (store_fpr): Remove #ifdef'd out call to UndefinedResult which wouldn't compile anyway. * sim-main.h (unpredictable_action): New function prototype. (Unpredictable): Define to call igen function unpredictable(). (NotWordValue): New macro to call igen function not_word_value(). (UndefinedResult): Remove. * interp.c (undefined_result): Remove. (unpredictable_action): New function. * mips.igen (not_word_value, unpredictable): New functions. (ADD, ADDI, do_addiu, do_addu, BGEZAL, BGEZALL, BLTZAL, BLTZALL) (CLO, CLZ, MADD, MADDU, MSUB, MSUBU, MUL, do_mult, do_multu) (do_sra, do_srav, do_srl, do_srlv, SUB, do_subu): Invoke NotWordValue() to check for unpredictable inputs, then Unpredictable() to handle them.
2002-03-062002-03-05 Chris Demetriou <cgd@broadcom.com>Chris Demetriou1-0/+3
* sim-main.h (UndefinedResult, Unpredictable): New macros which currently do nothing.
2002-03-062002-03-05 Chris Demetriou <cgd@broadcom.com>Chris Demetriou1-2/+21
* sim-main.h (status_UX, status_SX, status_KX, status_TS) (status_PX, status_MX, status_CU0, status_CU1, status_CU2) (status_CU3): New definitions. * sim-main.h (ExceptionCause): Add new values for MIPS32 and MIPS64: MDMX, MCheck, CacheErr. Update comments for DebugBreakPoint and NMIReset to note their status in MIPS32 and MIPS64. (SignalExceptionMDMX, SignalExceptionWatch, SignalExceptionMCheck) (SignalExceptionCacheErr): New exception macros.
2002-03-062002-03-05 Chris Demetriou <cgd@broadcom.com>Chris Demetriou1-1/+4
* mips.igen (check_fpu): Enable check for coprocessor 1 usability. * sim-main.h (COP_Usable): Define, but for now coprocessor 1 is always enabled. (SignalExceptionCoProcessorUnusable): Take as argument the unusable coprocessor number.
2002-03-052002-02-05 Chris Demetriou <cgd@broadcom.com>Chris Demetriou1-9/+0
* sim-main.h (SIGNEXTEND): Remove.
2001-11-18 2001-11-17 Fred Fish <fnf@redhat.com>Fred Fish1-7/+7
* sim-main.h (float_operation): Move enum declaration outside of _sim_cpu struct declaration.
2001-04-12* mips.igen (CFC1, CTC1): Pass the correct register numbers toJim Blandy1-1/+0
PENDING_FILL. Use PENDING_SCHED directly to handle the pending set of the FCSR. * sim-main.h (COCIDX): Remove definition; this isn't supported by PENDING_FILL, and you can get the intended effect gracefully by calling PENDING_SCHED directly.
2001-02-242001-02-23 Ben Elliston <bje@redhat.com>Ben Elliston1-0/+2
* sim-main.h (ENGINE_ISSUE_PREFIX_HOOK): Only define if not already defined elsewhere.
2001-02-192001-02-19 Ben Elliston <bje@redhat.com>Ben Elliston1-1/+1
* sim-main.h (sim_monitor): Return an int. * interp.c (sim_monitor): Add return values. (signal_exception): Handle error conditions from sim_monitor.
2000-10-19* cleanupFrank Ch. Eigler1-5/+0
2000-10-19 Frank Ch. Eigler <fche@redhat.com> On advice from Chris G. Demetriou <cgd@sibyte.com>: * sim-main.h (GPR_CLEAR): Remove unused alternative macro.
2000-05-29Define GPR_CLEARNick Clifton1-0/+7
1999-04-16Initial creation of sourceware repositorygdb-4_18-branchpointStan Shebs1-0/+785
1999-04-16Initial creation of sourceware repositoryStan Shebs1-1209/+0
1998-12-30* eCos->devo merge; tx3904 sanitize tags removedFrank Ch. Eigler1-4/+30
1998-12-29 Frank Ch. Eigler <fche@cygnus.com> * interp.c (sim_open): Allocate jm3904 memory in smaller chunks. (load_word): Call SIM_CORE_SIGNAL hook on error. (signal_exception): Call SIM_CPU_EXCEPTION_TRIGGER hook before starting. For exception dispatching, pass PC instead of NULL_CIA. (decode_coproc): Use COP0_BADVADDR to store faulting address. * sim-main.h (COP0_BADVADDR): Define. (SIM_CORE_SIGNAL): Define hook to call mips_core_signal. (SIM_CPU_EXCEPTION*): Define hooks to call mips_cpu_exception*(). (_sim_cpu): Add exc_* fields to store register value snapshots. * mips.igen (*): Replace memory-related SignalException* calls with references to SIM_CORE_SIGNAL hook. * dv-tx3904irc.c (tx3904irc_port_event): printf format warning fix. * sim-main.c (*): Minor warning cleanups.
1998-12-08* sky->devo merge, final part of sim mergeFrank Ch. Eigler1-27/+18
[ChangeLog.sky] 1998-12-08 Frank Ch. Eigler <fche@cygnus.com> * sim-main.h (sim_state): Add multi-phase load tracking fields. * sky-gdb.c (sky_option_handler): Add --load-next option handling. * mips.igen (BREAK): Add multi-phase load and printf code handling.
1998-11-23Switch mips-lsi-elf mips16 simulator to igen (from gencode).Andrew Cagney1-2/+2
1998-11-12Add configury for mips-lsi-elf target (32 bit MIPS16).Andrew Cagney1-4/+12
Fix numerous problems with PENDING_* code. In old gencode simulator, don't double tick each cycle. Add BREAK instruction to MIPS16 gencode simulator.
1998-10-27* MONSTER sky -> devo mergeFrank Ch. Eigler1-46/+134
* ChangeLog / ChangeLog.sky entries were merged with original time stamps; a few were moved between the files
1998-09-08* Patch for PR 17142, brought over from sky branch.Frank Ch. Eigler1-6/+21
Fri Sep 4 10:37:57 1998 Frank Ch. Eigler <fche@cygnus.com> * r5900.igen (mtsab): Correct typo in input register. * sim-main.h (TMP_*): New macros for accessing local 128-bit temporary for multimedia instructions. * r5900.igen (*): Convert most instructions to use new TMP macros to store output result during computation.
1998-07-31 * sim-main.h: shadow NUM_CORE_REGS from tm-txvu.hRon Unrau1-6/+14
* interp.c: use NUM_CORE_REGS * sky-gdb.c (set_fifo_breakpoints): use VIF interrupt bit for break * sky-pke.c (pke_issue): use interrupt bit for break points
1998-06-29 * interp.c (OPTION_BRANCH_BUG_4011): Add.Gavin Romig-Koch1-1/+39
(mips_option_handler): Handle OPTION_BRANCH_BUG_4011. (mips_options): Define the option. * mips.igen (check_4011_branch_bug): New. (mark_4011_branch_bug): New. (all branch insn): Call mark_branch_bug, and check_branch_bug. * sim-main.h (branchbug4011_option, branchbug4011_last_target, branchbug4011_last_cia, BRANCHBUG4011_OPTION, BRANCHBUG4011_LAST_TARGET, BRANCHBUG4011_LAST_CIA, check_branch_bug, mark_branch_bug): Define.
1998-06-16 * sky-pke.c(read_pke_pc): return source address of current pcRon Unrau1-2/+15
* sky-pke.c(read_pke_pcx): return index of current pc * sky-pke.h: export read_pke_pcx * interp.c(sim_fetch_registers): read pke pc/pcx * sky-libvpe.c: track name change from GDB * sim-main.h: add vif memory based pc - extend gdb comm area for fifo breakpoints - define SIM_ENGINE_RESTART_HOOK * sky-gdb.c: add support for VIF breakpoints
1998-06-14 * sky-engine.c: Set ordering of device issues to match enumerated typeRon Unrau1-7/+7
txvu_cpu_context (sim-main.h tm-txvu.h). This also allowed the issue structure to be simplified to an array of functions.
1998-06-09* Handle 10 and 20-bit versions of Break instruction. Move handlingIan Carmichael1-1/+19
* of special values from signal_exception() in interp.c into mips.igen. * * Modified: gencode.c interp.c mips.igen sim-main.h
1998-05-18* Monster patch - may destablize MIPS sims for a little while.Frank Ch. Eigler1-7/+72
* Followup patch for SCEI PR 15853 * First check-in of TX3904 interrupt controller devices for ECC. [sanitized] * First implementation of MIPS hardware interrupt emulation. Mon May 18 18:22:42 1998 Frank Ch. Eigler <fche@cygnus.com> * configure.in (SIM_AC_OPTION_HARDWARE): Added common hardware modules. Recognize TX39 target with "mips*tx39" pattern. * configure: Rebuilt. * sim-main.h (*): Added many macros defining bits in TX39 control registers. (SignalInterrupt): Send actual PC instead of NULL. (SignalNMIReset): New exception type. * interp.c (board): New variable for future use to identify a particular board being simulated. (mips_option_handler,mips_options): Added "--board" option. (interrupt_event): Send actual PC. (sim_open): Make memory layout conditional on board setting. (signal_exception): Initial implementation of hardware interrupt handling. Accept another break instruction variant for simulator exit. (decode_coproc): Implement RFE instruction for TX39. (mips.igen): Decode RFE instruction as such. start-sanitize-tx3904 * configure.in (tx3904cpu,tx3904irc): Added devices for tx3904. * interp.c: Define "jmr3904" and "jmr3904debug" board types and bbegin to implement memory map. * dv-tx3904cpu.c: New file. * dv-tx3904irc.c: New file. end-sanitize-tx3904
1998-05-07 * sim-main.h (INSN_NAME): New arg `cpu'.Doug Evans1-2/+8
1998-04-29 * sim-main.h, sky-libvpe.c: r59fp_op* functions were called withJames Lemke1-11/+12
1st parm of wrong type. Converted remaining "/" to "FDiv". * interp.c: Make "--float-type host" the default.
1998-04-22Move target specific stuff from sim/common/sim-base.h to sim/mips/sim-main.hJames Lemke1-0/+11
1998-04-21r5900.igen, sim-main.h, sky-libvpe.c: Add run-time option --float-typeJames Lemke1-0/+19
1998-04-21Fix sanitize tag. The proper keyword is "start-sanitize-*", notJason Molenda1-2/+2
"begin-sanitize-*".
1998-04-21For new IGEN simulators, rewrite checks validating correct use of theAndrew Cagney1-37/+47
HI/LO registers. For old gencode simulator, delete all checks.
generated by cgit v1.1 at 2024-07-13 12:29:06 +0000