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2016-11-11sim: mips: fix builds for r3900 cpus due to missing check_u64Mike Frysinger1-0/+1
2015-12-26sim: mips: delete mmu stubs to move to common sim_{read,write}Mike Frysinger1-163/+102
The only unique thing about mip's sim_{read,write} helpers is the call to address_translation on the incoming address. When we look closer at that function though, we see it's just a stub that maps physical to virtual, and the cache/return values are hardcoded. If we delete this function, we can then collapse all the callers and drop the custom sim_{read,write} logic entirely. Some day we might want to add MMU support, but when we do, we'll want to have the common layers handle things so all targets benefit.
2015-09-25[PATCH] Add micromips support to the MIPS simulatorAndrew Bennett1-807/+1428
2015-09-25 Andrew Bennett <andrew.bennett@imgtec.com> Ali Lown <ali.lown@imgtec.com> sim/common/ * sim-bits.h (EXTEND6): New macro. (EXTEND12): New macro. (EXTEND25): New macro. sim/mips/ * Makefile.in (tmp-micromips): New rule. (tmp-mach-multi): Add support for micromips. * configure.ac (mips*-sde-elf* | mips*-mti-elf*): Made a multi sim that works for both mips64 and micromips64. (mipsisa32r2*-*-*): Made a multi sim that works for mips32 and micromips32. Add build support for micromips. * dsp.igen (do_ph_s_absq, do_w_s_absq, do_qb_s_absq, do_addsc, do_addwc, do_bitrev, do_extpv, do_extrv, do_extrv_s_h, do_insv, do_lxx do_modsub, do_mthlip, do_mulsaq_s_w_ph, do_ph_packrl, do_qb_pick do_ph_pick, do_qb_ph_precequ, do_qb_ph_preceu, do_w_preceq do_w_ph_precrq, do_ph_qb_precrq, do_w_ph_rs_precrq do_qb_w_raddu, do_rddsp, do_repl, do_shilov, do_ph_shl, do_qb_shl do_w_s_shllv, do_ph_shrlv, do_w_r_shrav, do_wrdsp, do_qb_shrav, do_append, do_balign, do_ph_w_mulsa, do_ph_qb_precr, do_prepend): New functions. Refactored instruction code to use these functions. * dsp2.igen: Refactored instruction code to use the new functions. * interp.c (decode_coproc): Refactored to work with any instruction encoding. (isa_mode): New variable (RSVD_INSTRUCTION): Changed to 0x00000039. * m16.igen (BREAK16): Refactored instruction to use do_break16. (JALX32): Add mips32, mips64, mips32r2 and mips64r2 models. * micromips.dc: New file. * micromips.igen: New file. * micromips16.dc: New file. * micromipsdsp.igen: New file. * micromipsrun.c: New file. * mips.igen (do_swc1): Changed to work with any instruction encoding. (do_add do_addi do_andi do_dadd do_daddi do_dsll32 do_dsra32 do_dsrl32, do_dsub, do_break, do_break16, do_clo, do_clz, do_dclo do_dclz, do_lb, do_lh, do_lwr, do_lwl, do_lwc, do_lw, do_lwu, do_lhu do_ldc, do_lbu, do_ll, do_lld, do_lui, do_madd, do_dsp_madd, do_maddu do_dsp_maddu, do_dsp_mfhi, do_dsp_mflo, do_movn, do_movz, do_msub do_dsp_msub, do_msubu, do_dsp_msubu, do_mthi, do_dsp_mthi, do_mtlo do_dsp_mtlo, do_mul, do_dsp_mult, do_dsp_multu, do_pref, do_sc, do_scd do_sub, do_sw, do_teq, do_teqi, do_tge, do_tgei, do_tgeiu, do_tgeu, do_tlt do_tlti, do_tltiu, do_tltu, do_tne, do_tnei, do_abs_fmt, do_add_fmt do_alnv_ps, do_c_cond_fmt, do_ceil_fmt, do_cfc1, do_ctc1, do_cvt_d_fmt do_cvt_l_fmt, do_cvt_ps_s, do_cvt_s_fmt, do_cvt_s_pl, do_cvt_s_pu do_cvt_w_fmt, do_div_fmt, do_dmfc1b, do_dmtc1b, do_floor_fmt, do_luxc1_32 do_luxc1_64, do_lwc1, do_lwxc1, do_madd_fmt, do_mfc1b, do_mov_fmt, do_movtf do_movtf_fmt, do_movn_fmt, do_movz_fmt, do_msub_fmt, do_mtc1b, do_mul_fmt do_neg_fmt, do_nmadd_fmt, do_nmsub_fmt, do_pll_ps, do_plu_ps, do_pul_ps do_puu_ps, do_recip_fmt, do_round_fmt, do_rsqrt_fmt, do_prefx, do_sdc1 do_suxc1_32, do_suxc1_64, do_sqrt_fmt, do_sub_fmt, do_swc1, do_swxc1 do_trunc_fmt): New functions, refactored from existing instructions. Refactored instruction code to use these functions. (RSVD): Changed to use new reserved instruction. (loadstore_ea, not_word_value, unpredictable, check_mt_hilo, check_mf_hilo, check_mult_hilo, check_div_hilo, check_u64, do_luxc1_32, do_sdc1, do_suxc1_32, check_fmt_p, check_fpu, do_load_double, do_store_double): Added micromips32 and micromips64 models. Added include for micromips.igen and micromipsdsp.igen Add micromips32 and micromips64 models. (DecodeCoproc): Updated to use new macro definition. * mips3264r2.igen (do_dsbh, do_dshd, do_dext, do_dextm, do_dextu, do_di, do_dins, do_dinsm, do_ei, do_ext, do_mfhc1, do_mthc1, do_ins, do_dinsu, do_seb, do_seh do_rdhwr, do_wsbh): New functions. Refactored instruction code to use these functions. * sim-main.h (CP0_operation): New enum. (DecodeCoproc): Updated macro. (IMEM32_MICROMIPS, IMEM16_MICROMIPS, MICROMIPS_MINOR_OPCODE, MICROMIPS_DELAYSLOT_SIZE_ANY, MICROMIPS_DELAYSLOT_SIZE_16, MICROMIPS_DELAYSLOT_SIZE_32, ISA_MODE_MIPS32 and ISA_MODE_MICROMIPS): New defines. (sim_state): Add isa_mode field. sim/testsuite/sim/mips/ * basic.exp (run_micromips_test, run_sim_tests): New functions Add support for micromips tests. * hilo-hazard-4.s: New file. * testutils.inc (_dowrite): Changed reserved instruction encoding. (writemsg): Moved the la and li instructions before the data they are assigned to, which prevents a bug where MIPS32 relocations are used instead of micromips relocations when building for micromips.
2007-10-22sim/mips/Richard Sandiford1-23/+82
* mips.igen (check_fmt_p): Provide a separate mips32r2 definition that unconditionally allows fmt_ps. (ALNV.PS, CEIL.L.fmt, CVT.L.fmt, CVT.PS.S, CVT.S.PL, CVT.S.PU) (FLOOR.L.fmt, LWXC1, MADD.fmt, MSUB.fmt, NMADD.fmt, NMSUB.fmt) (PLL.PS, PLU.PS, PUL.PS, PUU.PS, ROUND.L.fmt, TRUNC.L.fmt): Change filter from 64,f to 32,f. (PREFX): Change filter from 64 to 32. (LDXC1, LUXC1): Provide separate mips32r2 implementations that use do_load_double instead of do_load. Make both LUXC1 versions unpredictable if SizeFGR () != 64. (SDXC1, SUXC1): Extend to mips32r2, using do_store_double instead of do_store. Remove unused variable. Make both SUXC1 versions unpredictable if SizeFGR () != 64.
2007-10-07sim/mips/Richard Sandiford1-7/+11
* mips.igen (ll): Fix mask for WITH_TARGET_WORD_BITSIZE == 32. (sc, swxc1): Likewise. Also fix big-endian and reverse-endian shifts for that case.
2007-05-14 * mips.igen (ALNV.PS, CEIL.L.fmt, CVT.L.fmt, CVT.PS.S, CVT.S.PL,Thiemo Seufer1-0/+24
CVT.S.PU, FLOOR.L.fmt, LDXC1, LUXC1, LWXC1, MADD.fmt, MSUB.fmt, NMADD.fmt, NMSUB.fmt, PLL.PS, PLU.PS, PREFX, PUL.PS, PUU.PS, RECIP.fmt, ROUND.L.fmt, RSQRT.fmt, SWXC1, TRUNC.L.fmt): Add support for mips32r2.
2007-03-01 * mips.igen (MFHI, MFLO, MTHI, MTLO): Restore support for mips32Thiemo Seufer1-0/+8
and mips64.
2007-02-20 [ gas/ChangeLog ]Thiemo Seufer1-12/+187
* config/tc-mips.c (mips_set_options, mips_opts, file_ase_dspr2, ISA_SUPPORTS_DSPR2_ASE, MIPS_CPU_ASE_DSPR2): Add DSP R2 ASE support. (macro_build): Add case '2'. (macro): Expand M_BALIGN to nop, packrl.ph or balign. (validate_mips_insn): Add support for balign instruction. (mips_ip): Handle DSP R2 instructions. Support balign instruction. (OPTION_DSPR2, OPTION_NO_DSPR2, OPTION_COMPAT_ARCH_BASE, md_parse_option, mips_after_parse_args): Add -mdspr2 and -mno-dspr2 command line options. (s_mipsset): Add support for .set dspr2 and .set nodspr2 directives. (md_show_usage): Add -mdspr2 and -mno-dspr2 help output. * doc/c-mips.texi, doc/as.texinfo: Document -mdspr2, -mno-dspr2, .set dspr2, .set nodspr2. [ gas/testsuite/ChangeLog ] * gas/mips/mips32-dspr2.s, gas/mips/mips32-dspr2.d: New test for DSP R2. * gas/mips/mips.exp: Run new test. [ include/opcode/Changelog ] * mips.h (OP_SH_BP, OP_MASK_BP): Add support for balign instruction. (INSN_DSPR2): Add flag for DSP R2 instructions. (M_BALIGN): New macro. [ opcodes/ChangeLog ] * mips-dis.c (mips_arch_choices): Add DSP R2 support. (print_insn_args): Add support for balign instruction. * mips-opc.c (D33): New shortcut for DSP R2 instructions. (mips_builtin_opcodes): Add DSP R2 instructions. [ sim/mips/ChangeLog ] * Makefile.in (IGEN_INCLUDE): Add dsp2.igen. * configure.ac (mips*-sde-elf*, mipsisa32r2*-*-*, mipsisa64r2*-*-*): Add dsp2 to sim_igen_machine. * configure: Regenerate. * dsp.igen (do_ph_op): Add MUL support when op = 2. (do_ph_mulq): New function to support mulq_rs.ph and mulq_s.ph. (mulq_rs.ph): Use do_ph_mulq. (MFHI, MFLO, MTHI, MTLO): Move these instructions to mips.igen. * mips.igen: Add dsp2 model and include dsp2.igen. (MFHI, MFLO, MTHI, MTLO): Extend these instructions for for *mips32r2, *mips64r2, *dsp. (MADD, MADDU, MSUB, MSUBU, MULT, MULTU): Extend these instructions for *mips32r2, *mips64r2, *dsp2. * dsp2.igen: New file for MIPS DSP REV 2 ASE. [ sim/testsuite/sim/mips/ChangeLog ] * basic.exp: Run the dsp2 test. * utils-dsp.inc (dspckacc_astio, dspck_tsimm): New macro. * mips32-dsp2.s: New test.
2007-02-19 * mips.igen (jalr.hb, jr.hb): Add decoder for mip32r2/mips64r2Thiemo Seufer1-1/+18
jumps with hazard barrier.
2007-02-19 * cp1.c (value_fpr): Don't inherit existing FPR_STATE forThiemo Seufer1-16/+5
uninterpreted formats. If fmt is one of the uninterpreted types don't update the FPR_STATE. Handle fmt_uninterpreted_32 like fmt_word, and fmt_uninterpreted_64 like fmt_long. (store_fpr): When writing an invalid odd register, set the matching even register to fmt_unknown, not the following register. * interp.c (sim_open): If STATE_MEM_SIZE isn't set then set it to the the memory window at offset 0 set by --memory-size command line option. (sim_store_register): Handle storing 4 bytes to an 8 byte floating point register. (sim_fetch_register): Likewise for reading 4 bytes from an 8 byte register. (sim_monitor): When returning the memory size to the MIPS application, use the value in STATE_MEM_SIZE, not an arbitrary hardcoded value. (cop_lw): Don' mess around with FPR_STATE, just pass fmt_uninterpreted_32 to StoreFPR. (cop_sw): Similarly. (cop_ld): Pass fmt_uninterpreted_64 not fmt_uninterpreted. (cop_sd): Similarly. * mips.igen (not_word_value): Single version for mips32, mips64 and mips16.
2006-08-29 * configure.ac (mipsisa32r2*-*-*, mipsisa32*-*-*): Add smartmips toThiemo Seufer1-0/+6
sim_igen_machine. * configure: Regenerate. * mips.igen (model): Add smartmips. (MADDU): Increment ACX if carry. (do_mult): Clear ACX. (ROR,RORV): Add smartmips. (include): Include smartmips.igen. * sim-main.h (ACX): Set to REGISTERS[89]. * smartmips.igen: New file.
2005-12-14* Makefile.in (SIM_OBJS): Add dsp.o.Chao-ying Fu1-16/+2
(dsp.o): New dependency. (IGEN_INCLUDE): Add dsp.igen. * configure.ac (mipsisa32r2*-*-*, mipsisa32*-*-*, mipsisa64r2*-*-*, mipsisa64*-*-*): Add dsp to sim_igen_machine. * configure: Regenerate. * mips.igen: Add dsp model and include dsp.igen. (MFHI, MFLO, MTHI, MTLO): Remove mips32, mips32r2, mips64, mips64r2, because these instructions are extended in DSP ASE. * sim-main.h (LAST_EMBED_REGNUM): Change from 89 to 96 because of adding 6 DSP accumulator registers and 1 DSP control register. (AC0LOIDX, AC0HIIDX, AC1LOIDX, AC1HIIDX, AC2LOIDX, AC2HIIDX, AC3LOIDX, AC3HIIDX, DSPLO, DSPHI, DSPCRIDX, DSPCR, DSPCR_POS_SHIFT, DSPCR_POS_MASK, DSPCR_POS_SMASK, DSPCR_SCOUNT_SHIFT, DSPCR_SCOUNT_MASK, DSPCR_SCOUNT_SMASK, DSPCR_CARRY_SHIFT, DSPCR_CARRY_MASK, DSPCR_CARRY_SMASK, DSPCR_CARRY, DSPCR_EFI_SHIFT, DSPCR_EFI_MASK, DSPCR_EFI_SMASK, DSPCR_EFI, DSPCR_OUFLAG_SHIFT, DSPCR_OUFLAG_MASK, DSPCR_OUFLAG_SMASK, DSPCR_OUFLAG4, DSPCR_OUFLAG5, DSPCR_OUFLAG6, DSPCR_OUFLAG7, DSPCR_CCOND_SHIFT, DSPCR_CCOND_MASK, DSPCR_CCOND_SMASK): New define. (DSPLO_REGNUM, DSPHI_REGNUM): New array for DSP accumulators. * dsp.c, dsp.igen: New files for MIPS DSP ASE.
2005-06-16* mips.igen: New mips16e model and include m16e.igen.David Ung1-0/+3
(check_u64): Add mips16e tag. * m16e.igen: New file for MIPS16e instructions. * configure.ac (mipsisa32*-*-*, mipsisa32r2*-*-*, mipsisa64*-*-*, mipsisa64r2*-*-*): Change sim_gen to M16, add mips16 and mips16e models. * configure: Regenerate.
2005-05-262005-05-26 David Ung <davidu@mips.com>Chris Demetriou1-6/+439
* mips.igen (mips32r2, mips64r2): New ISA models. Add new model tags to all instructions which are applicable to the new ISAs. (do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Add, moved from vr.igen. * mips3264r2.igen: New file for MIPS 32/64 revision 2 specific instructions. * vr.igen (do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Move to mips.igen. * configure.ac (mipsisa32r2*-*-*, mipsisa64r2*-*-*): Add new targets. * configure: Regenerate.
2004-04-102004-04-09 Chris Demetriou <cgd@broadcom.com>Chris Demetriou1-62/+33
* mips.igen (check_fmt): Remove. (ABS.fmt, ADD.fmt, C.cond.fmta, C.cond.fmtb, CEIL.L.fmt, CEIL.W) (CVT.D.fmt, CVT.L.fmt, CVT.S.fmt, CVT.W.fmt, DIV.fmt, FLOOR.L.fmt) (FLOOR.W.fmt, MADD.fmt, MOV.fmt, MOVtf.fmt, MOVN.fmt, MOVZ.fmt) (MSUB.fmt, MUL.fmt, NEG.fmt, NMADD.fmt, NMSUB.fmt, RECIP.fmt) (ROUND.L.fmt, ROUND.W.fmt, RSQRT.fmt, SQRT.fmt, SUB.fmt) (TRUNC.L.fmt, TRUNC.W): Explicitly specify allowed FPU formats. (check_fmt_p, CEIL.L.fmt, CEIL.W, DIV.fmt, FLOOR.L.fmt) (FLOOR.W.fmt, RECIP.fmt, ROUND.L.fmt, ROUND.W.fmt, RSQRT.fmt) (SQRT.fmt, TRUNC.L.fmt, TRUNC.W): Remove all uses of check_fmt. (C.cnd.fmta): Remove incorrect call to check_fmt_p.
2004-03-29 * sim-main.h (MIPS_MACH_HAS_MT_HILO_HAZARD)Richard Sandiford1-13/+51
(MIPS_MACH_HAS_MULT_HILO_HAZARD, MIPS_MACH_HAS_DIV_HILO_HAZARD): New. * mips.igen (check_mt_hilo, check_mult_hilo, check_div_hilo): Provide separate implementations for mipsIV and mipsV. Use new macros to determine whether the restrictions apply.
2004-01-202004-01-19 Chris Demetriou <cgd@broadcom.com>Chris Demetriou1-11/+61
* mips.igen (check_mf_cycles, check_mt_hilo, check_mf_hilo) (check_mult_hilo): Improve comments. (check_div_hilo): Likewise. Also, fork off a new version to handle mips32/mips64 (since there are no hazards to check in MIPS32/MIPS64).
2003-06-182003-06-17 Richard Sandiford <rsandifo@redhat.com>Chris Demetriou1-2/+2
* mips.igen (do_dmultx): Fix check for negative operands.
2003-01-142003-01-14 Chris Demetriou <cgd@broadcom.com>Chris Demetriou1-0/+34
* mips.igen (LUXC1, SUXC1): New, for mipsV and mips64.
2003-01-142003-01-14 Chris Demetriou <cgd@broadcom.com>Chris Demetriou1-23/+0
* mips.igen (EI, DI): Remove.
2003-01-052003-01-04 Richard Sandiford <rsandifo@redhat.com>Chris Demetriou1-0/+12
Andrew Cagney <ac131313@redhat.com> Gavin Romig-Koch <gavin@redhat.com> Graydon Hoare <graydon@redhat.com> Aldy Hernandez <aldyh@redhat.com> Dave Brolley <brolley@redhat.com> Chris Demetriou <cgd@broadcom.com> * configure.in (mips64vr*): Define TARGET_ENABLE_FR to 1. (sim_mach_default): New variable. (mips64vr-*-*, mips64vrel-*-*): New configurations. Add a new simulator generator, MULTI. * configure: Regenerate. * Makefile.in (SIM_MULTI_OBJ, SIM_EXTRA_DISTCLEAN): New variables. (multi-run.o): New dependency. (SIM_MULTI_ALL, SIM_MULTI_IGEN_CONFIGS): New variables. (tmp-mach-multi, tmp-itable-multi, tmp-run-multi): New rules. (tmp-multi): Combine them. (BUILT_SRC_FROM_MULTI): New variable. Depend on tmp-multi. (clean-extra): Remove sources in BUILT_SRC_FROM_MULTI. (distclean-extra): New rule. * sim-main.h: Include bfd.h. (MIPS_MACH): New macro. * mips.igen (vr4120, vr5400, vr5500): New models. (clo, clz, dclo, dclz, madd, maddu, msub, msub, mul): Add *vr5500. * vr.igen: Replace with new version.
2002-12-312002-12-31 Chris Demetriou <cgd@broadcom.com>Chris Demetriou1-36/+0
* sim-main.h (check_branch_bug, mark_branch_bug): Remove. * mips.igen: Remove all invocations of check_branch_bug and mark_branch_bug.
2002-07-312002-07-30 Chris Demetriou <cgd@broadcom.com>Chris Demetriou1-4/+91
* mips.igen (do_load_double, do_store_double): New functions. (LDC1, SDC1): Rename to... (LDC1b, SDC1b): respectively. (LDC1a, SDC1a): New instructions for MIPS II and MIPS32 support.
2002-06-142002-06-14 Chris Demetriou <cgd@broadcom.com>Chris Demetriou1-1/+3
Ed Satterthwaite <ehs@broadcom.com> * mips3d.igen: New file which contains MIPS-3D ASE instructions. * Makefile.in (IGEN_INCLUDE): Add mips3d.igen. * mips.igen: Include mips3d.igen. (mips3d): New model name for MIPS-3D ASE instructions. (CVT.W.fmt): Don't use this instruction for word (source) format instructions. * cp1.c (fp_binary_r, fp_add_r, fp_mul_r, fpu_inv1, fpu_inv1_32) (fpu_inv1_64, fp_recip1, fp_recip2, fpu_inv_sqrt1, fpu_inv_sqrt1_32) (fpu_inv_sqrt1_64, fp_rsqrt1, fp_rsqrt2): New functions. (NR_FRAC_GUARD, IMPLICIT_1): New macros. * sim-main.h (fmt_pw, CompareAbs, AddR, MultiplyR, Recip1, Recip2) (RSquareRoot1, RSquareRoot2): New macros. (fp_add_r, fp_mul_r, fp_recip1, fp_recip2, fp_rsqrt1) (fp_rsqrt2): New functions. * configure.in: Add MIPS-3D support to mipsisa64 simulator. * configure: Regenerate.
2002-06-142002-06-13 Chris Demetriou <cgd@broadcom.com>Chris Demetriou1-11/+127
* cp1.c (FP_PS_upper, FP_PS_lower, FP_PS_cat, FPQNaN_PS): New macros. (value_fpr, store_fpr, fp_cmp, fp_unary, fp_binary, fp_mac) (fp_inv_sqrt, fpu_format_name): Add paired-single support. (convert): Note that this function is not used for paired-single format conversions. (ps_lower, ps_upper, pack_ps, convert_ps): New functions. * mips.igen (FMT, MOVtf.fmt): Add paired-single support. (check_fmt_p): Enable paired-single support. (ALNV.PS, CVT.PS.S, CVT.S.PL, CVT.S.PU, PLL.PS, PLU.PS, PUL.PS) (PUU.PS): New instructions. (CVT.S.fmt): Don't use this instruction for paired-single format destinations. * sim-main.h (FP_formats): New value 'fmt_ps.' (ps_lower, ps_upper, pack_ps, convert_ps): New prototypes. (PSLower, PSUpper, PackPS, ConvertPS): New macros.
2002-06-122002-06-12 Chris Demetriou <cgd@broadcom.com>Chris Demetriou1-41/+41
* mips.igen: Fix formatting of function calls in many FP operations.
2002-06-122002-06-12 Chris Demetriou <cgd@broadcom.com>Chris Demetriou1-4/+11
* mips.igen (MOVN, MOVZ): Trace result. (TNEI): Print "tnei" as the opcode name in traces. (CEIL.W): Add disassembly string for traces. (RSQRT.fmt): Make location of disassembly string consistent with other instructions.
2002-06-122002-06-12 Chris Demetriou <cgd@broadcom.com>Chris Demetriou1-10/+0
* mips.igen (X): Delete unused function.
2002-06-082002-06-07 Chris Demetriou <cgd@broadcom.com>Chris Demetriou1-74/+29
Ed Satterthwaite <ehs@broadcom.com> * cp1.c (inner_mac, fp_mac, inner_rsqrt, fp_inv_sqrt) (fp_rsqrt, fp_madd, fp_msub, fp_nmadd, fp_nmsub): New functions. * sim-main.h (fp_rsqrt, fp_madd, fp_msub, fp_nmadd) (fp_nmsub): New prototypes. (RSquareRoot, MultiplyAdd, MultiplySub, NegMultiplyAdd) (NegMultiplySub): New defines. * mips.igen (RSQRT.fmt): Use RSquareRoot(). (MADD.D, MADD.S): Replace with... (MADD.fmt): New instruction. (MSUB.D, MSUB.S): Replace with... (MSUB.fmt): New instruction. (NMADD.D, NMADD.S): Replace with... (NMADD.fmt): New instruction. (NMSUB.D, MSUB.S): Replace with... (NMSUB.fmt): New instruction.
2002-06-072002-06-06 Chris Demetriou <cgd@broadcom.com>Chris Demetriou1-177/+169
Ed Satterthwaite <ehs@broadcom.com> * cp1.h: New file. * sim-main.h: Include cp1.h. (SETFCC, GETFCC, IR, UF, OF, DX, IO, UO, FP_FLAGS, FP_ENABLE) (FP_CAUSE, GETFS, FP_RM_NEAREST, FP_RM_TOZERO, FP_RM_TOPINF) (FP_RM_TOMINF, GETRM): Remove. Moved to cp1.h. (FP_FS, FP_MASK_RM, FP_SH_RM, Nan, Less, Equal): Remove. (value_fcr, store_fcr, test_fcsr, fp_cmp): New prototypes. (ValueFCR, StoreFCR, TestFCSR, Compare): New macros. * cp1.c: Don't include sim-fpu.h; already included by sim-main.h. Clean up formatting of some comments. (NaN, Equal, Less): Remove. (test_fcsr, value_fcr, store_fcr, update_fcsr, fp_test) (fp_cmp): New functions. * mips.igen (do_c_cond_fmt): Remove. (C.cond.fmta, C.cond.fmtb): Replace uses of do_c_cond_fmt_a with Compare. Add result tracing. (CxC1): Remove, replace with... (CFC1a, CFC1b, CFC1c, CTC1a, CTC1b, CTC1c): New instructions. (DMxC1): Remove, replace with... (DMFC1a, DMFC1b, DMTC1a, DMTC1b): New instructions. (MxC1): Remove, replace with... (MFC1a, MFC1b, MTC1a, MTC1b): New instructions.
2002-06-042002-06-04 Chris Demetriou <cgd@broadcom.com>Chris Demetriou1-5/+5
* sim-main.h (FGRIDX): Remove, replace all uses with... (FGR_BASE): New macro. (FP0_REGNUM, FCRCS_REGNUM, FCRIR_REGNUM): New macros. (_sim_cpu): Move 'fgr' member to be right before 'fpr_state' member. (NR_FGR, FGR): Likewise. * interp.c: Replace all uses of FGRIDX with FGR_BASE. * mips.igen: Likewise.
2002-06-032002-06-03 Chris Demetriou <cgd@broadcom.com>Chris Demetriou1-0/+7
Ed Satterthwaite <ehs@broadcom.com> * configure.in (mipsisa64sb1*-*-*): New target for supporting Broadcom SiByte SB-1 processor configurations. * configure: Regenerate. * sb1.igen: New file. * mips.igen: Include sb1.igen. (sb1): New model. * Makefile.in (IGEN_INCLUDE): Add sb1.igen. * mdmx.igen: Add "sb1" model to all appropriate functions and instructions. * mdmx.c (AbsDiffOB, AvgOB, AccAbsDiffOB): New functions. (ob_func, ob_acc): Reference the above. (qh_acc): Adjust to keep the same size as ob_acc. * sim-main.h (status_SBX, MX_VECT_ABSD, MX_VECT_AVG, MX_AbsDiff) (MX_Avg, MX_VECT_ABSDA, MX_AbsDiffC): New macros.
2002-06-022002-06-02 Chris Demetriou <cgd@broadcom.com>Chris Demetriou1-0/+3
Ed Satterthwaite <ehs@broadcom.com> * mips.igen (mdmx): New (pseudo-)model. * mdmx.c, mdmx.igen: New files. * Makefile.in (SIM_OBJS): Add mdmx.o. * sim-main.h (MDMX_accumulator, MX_fmtsel, signed24, signed48): New typedefs. (ACC, MX_Add, MX_AddA, MX_AddL, MX_And, MX_C_EQ, MX_C_LT, MX_Comp) (MX_FMT_OB, MX_FMT_QH, MX_Max, MX_Min, MX_Msgn, MX_Mul, MX_MulA) (MX_MulL, MX_MulS, MX_MulSL, MX_Nor, MX_Or, MX_Pick, MX_RAC) (MX_RAC_H, MX_RAC_L, MX_RAC_M, MX_RNAS, MX_RNAU, MX_RND_AS) (MX_RND_AU, MX_RND_ES, MX_RND_EU, MX_RND_ZS, MX_RND_ZU, MX_RNES) (MX_RNEU, MX_RZS, MX_RZU, MX_SHFL, MX_ShiftLeftLogical) (MX_ShiftRightArith, MX_ShiftRightLogical, MX_Sub, MX_SubA, MX_SubL) (MX_VECT_ADD, MX_VECT_ADDA, MX_VECT_ADDL, MX_VECT_AND) (MX_VECT_MAX, MX_VECT_MIN, MX_VECT_MSGN, MX_VECT_MUL, MX_VECT_MULA) (MX_VECT_MULL, MX_VECT_MULS, MX_VECT_MULSL, MX_VECT_NOR) (MX_VECT_OR, MX_VECT_SLL, MX_VECT_SRA, MX_VECT_SRL, MX_VECT_SUB) (MX_VECT_SUBA, MX_VECT_SUBL, MX_VECT_XOR, MX_WACH, MX_WACL, MX_Xor) (SIM_ARGS, SIM_STATE, UnpredictableResult, fmt_mdmx, ob_fmtsel) (qh_fmtsel): New macros. (_sim_cpu): New member "acc". (mdmx_acc_op, mdmx_cc_op, mdmx_cpr_op, mdmx_pick_op, mdmx_rac_op) (mdmx_round_op, mdmx_shuffle, mdmx_wach, mdmx_wacl): New functions.
2002-05-012002-05-01 Chris Demetriou <cgd@broadcom.com>Chris Demetriou1-0/+110
* cp1.c (store_fpr): Remove #ifdef'd out call to UndefinedResult which wouldn't compile anyway. * sim-main.h (unpredictable_action): New function prototype. (Unpredictable): Define to call igen function unpredictable(). (NotWordValue): New macro to call igen function not_word_value(). (UndefinedResult): Remove. * interp.c (undefined_result): Remove. (unpredictable_action): New function. * mips.igen (not_word_value, unpredictable): New functions. (ADD, ADDI, do_addiu, do_addu, BGEZAL, BGEZALL, BLTZAL, BLTZALL) (CLO, CLZ, MADD, MADDU, MSUB, MSUBU, MUL, do_mult, do_multu) (do_sra, do_srav, do_srl, do_srlv, SUB, do_subu): Invoke NotWordValue() to check for unpredictable inputs, then Unpredictable() to handle them.
2002-04-252002-02-24 Chris Demetriou <cgd@broadcom.com>Chris Demetriou1-4/+4
* mips.igen: Fix formatting of calls to Unpredictable().
2002-03-122002-03-12 Chris Demetriou <cgd@broadcom.com>Chris Demetriou1-5/+546
* configure.in (mipsisa32*-*-*, mipsisa64*-*-*): New targets. * mips.igen (mips32, mips64): New models, add to all instructions and functions as appropriate. (loadstore_ea, check_u64): New variant for model mips64. (check_fmt_p): New variant for models mipsV and mips64, remove mipsV model marking fro other variant. (SLL) Rename to... (SLLa) this. (CLO, CLZ, MADD, MADDU, MSUB, MSUBU, MUL, SLLb): New instructions for mips32 and mips64. (DCLO, DCLZ): New instructions for mips64.
2002-03-082002-03-07 Chris Demetriou <cgd@broadcom.com>Chris Demetriou1-6/+6
* mips.igen (BREAK, LUI, ORI, SYSCALL, XORI): Print immediate or code as a hex value with the "%#lx" format. (ANDI): Likewise, and fix printed instruction name.
2002-03-062002-03-05 Chris Demetriou <cgd@broadcom.com>Chris Demetriou1-2/+0
* mips.igen (check_fpu): Enable check for coprocessor 1 usability. * sim-main.h (COP_Usable): Define, but for now coprocessor 1 is always enabled. (SignalExceptionCoProcessorUnusable): Take as argument the unusable coprocessor number.
2002-03-052002-03-05 Chris Demetriou <cgd@broadcom.com>Chris Demetriou1-19/+19
* mips.igen: Fix formatting of all SignalException calls.
2002-03-052002-02-04 Chris Demetriou <cgd@broadcom.com>Chris Demetriou1-5/+1
* mips.igen: Remove gencode comment from top of file, fix spelling in another comment.
2002-03-052002-02-04 Chris Demetriou <cgd@broadcom.com>Chris Demetriou1-132/+104
* mips.igen (check_fmt, check_fmt_p): New functions to check whether specific floating point formats are usable. (ABS.fmt, ADD.fmt, CEIL.L.fmt, CEIL.W, DIV.fmt, FLOOR.L.fmt) (FLOOR.W.fmt, MOV.fmt, MUL.fmt, NEG.fmt, RECIP.fmt, ROUND.L.fmt) (ROUND.W.fmt, RSQRT.fmt, SQRT.fmt, SUB.fmt, TRUNC.L.fmt, TRUNC.W): Use the new functions. (do_c_cond_fmt): Remove format checks... (C.cond.fmta, C.cond.fmtb): And move them into all callers.
2002-03-042002-02-03 Chris Demetriou <cgd@broadcom.com>Chris Demetriou1-52/+52
* mips.igen: Fix formatting of check_fpu calls.
2002-03-042002-03-03 Chris Demetriou <cgd@broadcom.com>Chris Demetriou1-1/+1
* mips.igen (FLOOR.L.fmt): Store correct destination register.
2002-03-042002-03-03 Chris Demetriou <cgd@broadcom.com>Chris Demetriou1-12/+12
* mips.igen: Remove whitespace at end of lines.
2002-03-032002-03-02 Chris Demetriou <cgd@broadcom.com>Chris Demetriou1-16/+37
* mips.igen (loadstore_ea): New function to do effective address calculations. (do_load, do_load_left, do_load_right, LL, LDD, PREF, do_store, do_store_left, do_store_right, SC, SCD, PREFX, SWC1, SWXC1, CACHE): Use loadstore_ea to do effective address computations.
2002-03-032002-03-02 Chris Demetriou <cgd@broadcom.com>Chris Demetriou1-7/+7
* interp.c (load_word): Use EXTEND32 rather than SIGNEXTEND. * mips.igen (LL, CxC1, MxC1): Likewise.
2002-03-032002-03-02 Chris Demetriou <cgd@broadcom.com>Chris Demetriou1-276/+134
* mips.igen (LL, LLD, PREF, SC, SCD, ABS.fmt, ADD.fmt, CEIL.L.fmt, CEIL.W, CVT.D.fmt, CVT.L.fmt, CVT.S.fmt, CVT.W.fmt, DIV.fmt, FLOOR.L.fmt, FLOOR.W.fmt, MADD.D, MADD.S, MOV.fmt, MOVtf.fmt, MSUB.D, MSUB.S, MUL.fmt, NEG.fmt, NMADD.D, NMADD.S, NMSUB.D, NMSUB.S, PREFX, RECIP.fmt, ROUND.L.fmt, ROUND.W.fmt, RSQRT.fmt, SQRT.fmt, SUB.fmt, SWC1, SWXC1, TRUNC.L.fmt, TRUNC.W, CACHE): Don't split opcode fields by hand, use the opcode field values provided by igen.
2002-03-012002-03-01 Chris Demetriou <cgd@broadcom.com>Chris Demetriou1-14/+13
* mips.igen (do_divu): Fix spacing. * mips.igen (do_dsllv): Move to be right before DSLLV, to match the rest of the do_<shift> functions.
2002-03-012002-03-01 Chris Demetriou <cgd@broadcom.com>Chris Demetriou1-0/+16
* mips.igen (do_dsll, do_dsllv, DSLL32, do_dsra, DSRA32, do_dsrl, DSRL32, do_dsrlv): Trace inputs and results.
2002-03-012002-03-01 Chris Demetriou <cgd@broadcom.com>Chris Demetriou1-0/+1
* mips.igen (CACHE): Provide instruction-printing string. * interp.c (signal_exception): Comment tokens after #endif.
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