| Age | Commit message (Expand) | Author | Files | Lines |
|---|
| 2001-04-12 | * mips.igen (CFC1, CTC1): Pass the correct register numbers to | Jim Blandy | 1 | -3/+3 |
| 2000-07-04 | Fix MOVN.fmt and MOVZ.fmt, need to test GPR[RT]. | Andrew Cagney | 1 | -14/+9 |
| 2000-06-23 | Fix printf arguments. | Andrew Cagney | 1 | -3/+4 |
| 2000-05-29 | fix spelling mistake in comment | Nick Clifton | 1 | -1/+1 |
| 2000-05-01 | * mips.igen (DMxC1): Fix format arguments for sim_io_eprintf call. | Andrew Cagney | 1 | -1/+2 |
| 2000-03-02 | * autoconf correction | Frank Ch. Eigler | 1 | -3/+19 |
| 1999-12-07 | import gdb-1999-12-06 snapshot | Jason Molenda | 1 | -0/+2 |
| 1999-10-26 | import gdb-1999-10-25 snapshot | Jason Molenda | 1 | -4/+3 |
| 1999-09-13 | import gdb-1999-09-13 snapshot | Jason Molenda | 1 | -2/+2 |
| 1999-09-09 | import gdb-1999-09-08 snapshot | Stan Shebs | 1 | -1/+2 |
| 1999-07-07 | import gdb-1999-07-07 pre reformat | Jason Molenda | 1 | -0/+18 |
| 1999-04-26 | import gdb-19990422 snapshot | Stan Shebs | 1 | -1/+9 |
| 1999-04-16 | Initial creation of sourceware repositorygdb-4_18-branchpoint | Stan Shebs | 1 | -0/+3895 |
| 1999-04-16 | Initial creation of sourceware repository | Stan Shebs | 1 | -6517/+0 |
| 1998-12-30 | * eCos->devo merge; tx3904 sanitize tags removed | Frank Ch. Eigler | 1 | -47/+95 |
| 1998-12-13 | for bfd: | Gavin Romig-Koch | 1 | -6/+499 |
| 1998-12-12 | * configure.in (mips64vr4xxx): Enable TARGET_ENABLE_FR. | Gavin Romig-Koch | 1 | -2/+2 |
| 1998-12-08 | * sky->devo merge, final part of sim merge | Frank Ch. Eigler | 1 | -4/+205 |
| 1998-11-23 | Configure mips64vr4100-elf nee mips64vr41* as a 64 bit mips16 igen simulator. | Andrew Cagney | 1 | -0/+3 |
| 1998-11-23 | Switch mips-lsi-elf mips16 simulator to igen (from gencode). | Andrew Cagney | 1 | -432/+476 |
| 1998-06-29 | * mips.igen (check_mf_hilo): Correct check. | Gavin Romig-Koch | 1 | -104/+5 |
| 1998-06-18 | * Adapt to changed R5900 SQC2 opcode. | Frank Ch. Eigler | 1 | -19/+46 |
| 1998-06-16 | * ECC (tx39) and sky changes. | Frank Ch. Eigler | 1 | -13/+19 |
| 1998-06-16 | Fix unresolved external error for sky_cpcond0 on non-SKY builds. | James Lemke | 1 | -0/+8 |
| 1998-06-15 | Implement CPCOND0 and insns BC0F/BC0FL/BC0T/BC0TL. | James Lemke | 1 | -0/+32 |
| 1998-06-09 | * Handle 10 and 20-bit versions of Break instruction. Move handling | Ian Carmichael | 1 | -0/+30 |
| 1998-06-09 | * mips.igen (SWC1) : Correct the handling of ReverseEndian | Gavin Romig-Koch | 1 | -6/+6 |
| 1998-06-04 | The r5900 doesn't have HI/LO DIV/MUL register problems. Hobble | Andrew Cagney | 1 | -27/+118 |
| 1998-05-21 | Fix sign extension on 32 bit add/sub instructions. | Andrew Cagney | 1 | -18/+42 |
| 1998-05-18 | * Monster patch - may destablize MIPS sims for a little while. | Frank Ch. Eigler | 1 | -0/+46 |
| 1998-05-13 | * mips/mips.igen (check_op_hilo,check_mult_hilo,check_div_hilo): | Gavin Romig-Koch | 1 | -9/+49 |
| 1998-04-21 | Implement ERET instruction. | Andrew Cagney | 1 | -0/+20 |
| 1998-04-21 | For new IGEN simulators, rewrite checks validating correct use of the | Andrew Cagney | 1 | -30/+96 |
| 1998-04-15 | Re-fix 32 bit DSRAV instruction. | Andrew Cagney | 1 | -6/+15 |
| 1998-04-15 | Debug tx19 built from igen sources. | Andrew Cagney | 1 | -10/+105 |
| 1998-04-14 | Implement 32 bit MIPS16 instructions listed in m16.igen. | Andrew Cagney | 1 | -112/+297 |
| 1998-04-05 | * R5900 COP2 function nearly complete. PKE sim now aware of new GPUIF | Frank Ch. Eigler | 1 | -819/+193 |
| 1998-04-02 | For mips get_mem_size call. Force the return of a 32 bit value | Andrew Cagney | 1 | -43/+0 |
| 1998-04-01 | * You bop one on the head ... another one appears. | Frank Ch. Eigler | 1 | -0/+4 |
| 1998-03-27 | * Inserted skeleton of R5900 COP2 simulation. Merged old vu[01].[ch] code | Frank Ch. Eigler | 1 | -11/+611 |
| 1998-03-03 | Fix DIV, DIV1 (wrong check for overflow) and DIVU1 (shouldn't check | Andrew Cagney | 1 | -2/+5 |
| 1998-02-25 | Finish implementation of r5900 instructions. | Andrew Cagney | 1 | -20/+24 |
| 1998-02-23 | sim-main.h: Re-arange r5900 registers so that they have their own | Andrew Cagney | 1 | -48/+45 |
| 1997-12-11 | * mips.igen (MSUB): Fix to work like MADD. | Jeff Law | 1 | -567/+465 |
| 1997-11-11 | Make the signess of compares between GPR's explicit using a cast to | Andrew Cagney | 1 | -59/+36 |
| 1997-11-11 | Fix IGEN version of MFC0, MTC0, SWC1, LWC1, SDC1, LDC1, LWXC1, | Andrew Cagney | 1 | -115/+369 |
| 1997-11-06 | IGEN likes to cache the current instruction address (CIA). Change the | Andrew Cagney | 1 | -23/+22 |
| 1997-11-05 | Rewrite the MIPS simulator's memory model so that it uses the generic | Andrew Cagney | 1 | -8/+8 |
| 1997-10-29 | common/sim-bits.h: Document ROTn macro. | Andrew Cagney | 1 | -15/+12 |
| 1997-10-28 | Add support for 16 byte quantities to sim-endian macro H2T. | Andrew Cagney | 1 | -26/+26 |
