| Age | Commit message (Expand) | Author | Files | Lines |
|---|
| 1998-05-21 | Fix sign extension on 32 bit add/sub instructions. | Andrew Cagney | 1 | -18/+42 |
| 1998-05-18 | * Monster patch - may destablize MIPS sims for a little while. | Frank Ch. Eigler | 1 | -0/+46 |
| 1998-05-13 | * mips/mips.igen (check_op_hilo,check_mult_hilo,check_div_hilo): | Gavin Romig-Koch | 1 | -9/+49 |
| 1998-04-21 | Implement ERET instruction. | Andrew Cagney | 1 | -0/+20 |
| 1998-04-21 | For new IGEN simulators, rewrite checks validating correct use of the | Andrew Cagney | 1 | -30/+96 |
| 1998-04-15 | Re-fix 32 bit DSRAV instruction. | Andrew Cagney | 1 | -6/+15 |
| 1998-04-15 | Debug tx19 built from igen sources. | Andrew Cagney | 1 | -10/+105 |
| 1998-04-14 | Implement 32 bit MIPS16 instructions listed in m16.igen. | Andrew Cagney | 1 | -112/+297 |
| 1998-04-05 | * R5900 COP2 function nearly complete. PKE sim now aware of new GPUIF | Frank Ch. Eigler | 1 | -819/+193 |
| 1998-04-02 | For mips get_mem_size call. Force the return of a 32 bit value | Andrew Cagney | 1 | -43/+0 |
| 1998-04-01 | * You bop one on the head ... another one appears. | Frank Ch. Eigler | 1 | -0/+4 |
| 1998-03-27 | * Inserted skeleton of R5900 COP2 simulation. Merged old vu[01].[ch] code | Frank Ch. Eigler | 1 | -11/+611 |
| 1998-03-03 | Fix DIV, DIV1 (wrong check for overflow) and DIVU1 (shouldn't check | Andrew Cagney | 1 | -2/+5 |
| 1998-02-25 | Finish implementation of r5900 instructions. | Andrew Cagney | 1 | -20/+24 |
| 1998-02-23 | sim-main.h: Re-arange r5900 registers so that they have their own | Andrew Cagney | 1 | -48/+45 |
| 1997-12-11 | * mips.igen (MSUB): Fix to work like MADD. | Jeff Law | 1 | -567/+465 |
| 1997-11-11 | Make the signess of compares between GPR's explicit using a cast to | Andrew Cagney | 1 | -59/+36 |
| 1997-11-11 | Fix IGEN version of MFC0, MTC0, SWC1, LWC1, SDC1, LDC1, LWXC1, | Andrew Cagney | 1 | -115/+369 |
| 1997-11-06 | IGEN likes to cache the current instruction address (CIA). Change the | Andrew Cagney | 1 | -23/+22 |
| 1997-11-05 | Rewrite the MIPS simulator's memory model so that it uses the generic | Andrew Cagney | 1 | -8/+8 |
| 1997-10-29 | common/sim-bits.h: Document ROTn macro. | Andrew Cagney | 1 | -15/+12 |
| 1997-10-28 | Add support for 16 byte quantities to sim-endian macro H2T. | Andrew Cagney | 1 | -26/+26 |
| 1997-10-27 | Separate r5900 specifoc and mips16 instructions. | Andrew Cagney | 1 | -5156/+5 |
| 1997-10-27 | Add mips64vr5400 to configuration list | Andrew Cagney | 1 | -1/+526 |
| 1997-10-24 | Checkpoint IGEN version of mips sim | Andrew Cagney | 1 | -152/+157 |
| 1997-10-16 | Checkpoint IGEN version of MIPS simulator. | Andrew Cagney | 1 | -248/+218 |
| 1997-10-14 | Checkpoint IGEN version of MIPS simulator. | Andrew Cagney | 1 | -1239/+1196 |
| 1997-10-09 | Snap. Gets through igen's checks. | Andrew Cagney | 1 | -322/+104 |
| 1997-10-08 | MIPS/IGEN checkpoint - doesn't build. | Andrew Cagney | 1 | -0/+9996 |
