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1998-04-21For new IGEN simulators, rewrite checks validating correct use of theAndrew Cagney1-15/+0
HI/LO registers. For old gencode simulator, delete all checks.
1997-12-11 * mips.igen (MSUB): Fix to work like MADD.Jeff Law1-1/+6
* gencode.c (MSUB): Similarly.
1997-11-06Replace global IPC with function argument cia or current instructionAndrew Cagney1-1/+1
address. Pass cia into calls to sim_engine_stop so that breakpoints et.al. work.
1997-10-29 * gencode.c: Add tx49 configury and insns.Gavin Romig-Koch1-6/+44
* configure.in: Add tx49 configury. * configure: Update.
1997-10-25 * sim/mips/gencode.c (build_instruction): Follow sim_write's lead in usingGavin Romig-Koch1-1/+1
BigEndianMem instead of !ByteSwapMem.
1997-10-24Add function to fetch 32bit instructionsAndrew Cagney1-8/+8
When address translation of insn fetch fails raise exception immediatly. Use address_word as type of all address variables (instead of unsigned64), the former is configured as either 32 or 64 bit type. Always compile fpu code (no #if has fpu)
1997-10-16Move register definitions and macros out of interp.c and into sim-main.hAndrew Cagney1-1/+1
1997-10-16* gencode.c (build_instruction): Use FPR_STATE not fpr_state.Andrew Cagney1-6/+6
1997-10-16* gencode.c (build_instruction): For "FPSQRT", output correct numberAndrew Cagney1-1/+3
of arguments to Recip.
1997-10-14o Add support for configuring wordsize, fp hardware and targetAndrew Cagney1-9/+9
endianness. Provide defaults for some tier-1 mips targets. o Parameterize all functions with SIM_DESC.
1997-09-25Add/use SIM_AC_OPTION_BITSIZE.Andrew Cagney1-10/+34
1997-09-25Allow gencode.c to generate input to the igen generator.Andrew Cagney1-201/+476
1997-09-20Add handling for 3900's SDBBP, DERET, and RFE insns.Gavin Romig-Koch1-7/+7
* gencode.c (SDBBP,DERET): Added (3900) insns. (RFE): Turn on for 3900. * interp.c (DebugBreakPoint,DEPC,Debug,Debug_*): Added. (dsstate): Made global. (SUBTARGET_R3900): Added. (CANCELDELAYSLOT): New. (SignalException): Ignore SystemCall rather than ignore and terminate. Add DebugBreakPoint handling. (decode_coproc): New insns RFE, DERET; and new registers Debug and DEPC protected by SUBTARGET_R3900. (sim_engine_run): Use CANCELDELAYSLOT rather than clearing bits explicitly. * Makefile.in,configure.in: Add mips subtarget option. * configure: Update.
1997-09-19 * gencode.c: Add r3900 (tx39).Gavin Romig-Koch1-21/+31
* gencode.c: Fix some configuration problems by improving the relationship between tx19 and tx39.
1997-09-16 * sim/mips/gencode.c (build_instruction): Don't need to subtract 4 forGavin Romig-Koch1-1/+2
JALR, just 2.
1997-09-09Remove GCC specific `0x...LL', replace with SIGNED64 (0x...).Andrew Cagney1-14/+11
1997-09-07tx19 and related necessary changes.Gavin Romig-Koch1-0/+9
* config.sub: Add tx19/r1900. * sim/mips/configure.in, sim/mips/gencode: Add tx19/r1900. * gcc/config.sub, gcc/configure: Add tx19/r1900. * gcc/config/mips/r1900.h, config/mips/t-r1900: New. * gas/config/tc-mips.c: Add tx19/r1900. * gcc/config/mips/mips.c: Don't build 16 bit to 32 bit stubs for TARGET_SOFT_FLOAT. * config.sub: Add "marketing-names" patch. * gcc/config.sub: Add "marketing-names" patch. * gcc/configure: Change "as" link from "../gas/as.new" to "../gas/as-new"; Same for "ld" link.
1997-09-01Test/fix pabsh, pabsw, psrlvw.Andrew Cagney1-5/+9
1997-08-25Add ABFD argument to sim_open call. Pass through to sim_config soAndrew Cagney1-3/+0
that image properties such as endianness can be checked. More strongly document the expected behavour of each of the sim_* interfaces. Add default endian argument to simulator config macro SIM_AC_OPTION_ENDIAN. Use in sim_config.
1997-07-28Handle overflow from signed divide by -1.Andrew Cagney1-5/+24
1997-07-25gencode.c: Two arg MADD should not assign result to /bin/bash.Gavin Romig-Koch1-1/+2
1997-07-11Fix a number of problems in the r5900 specific p* (parallel) instructions.Andrew Cagney1-88/+129
In particular a host endian dependency one fixed resolved most problems.
1997-07-02 * gencode.c (build_instruction): Handle "pext5" according toJeff Law1-1/+1
version 1.95 of the r5900 ISA. Fixes pr12413 (c/h from toshiba).
1997-07-02 * gencode.c (build_instruction): Handle "ppac5" according toJeff Law1-1/+1
version 1.95 of the r5900 ISA. fixes pr12407 (c/h from toshiba).
1997-07-02 * gencode.c (FEATURE_WARNINGS): Remove FEATURE_WARN_ZERO.Jeff Law1-2/+8
Fix for pr12402 (c/h from toshiba).
1997-06-02o Fix padd insnAndrew Cagney1-8/+12
o Take an interrupt when an int event occures.
1997-05-21Watchpoint interface.Andrew Cagney1-8/+8
1997-04-21for DIV: check for div by zero and int overflowGavin Romig-Koch1-15/+38
1997-02-26Correct the overloaded DOUBLEWORD problemGavin Romig-Koch1-7/+7
1997-02-25start-sanitize-r5900Dawn Perchik1-0/+2
* gencode.c: #ifdef out offending code until a permanent fix can be added. Code is causing build errors for non-5900 mips targets. end-sanitize-r5900
1997-02-20Correct test for ISA dependent bitsGavin Romig-Koch1-6/+18
1997-02-18Correct flags for PMADDUW insnGavin Romig-Koch1-1/+1
1997-02-13 * gencode.c (build_mips16_operands): Correct computation of baseIan Lance Taylor1-1/+1
address for extended PC relative instruction.
1997-02-11Add r5900Gavin Romig-Koch1-166/+1499
1997-02-04 * gencode.c (build_instruction): The high order may be set in theIan Lance Taylor1-1/+1
comparison flags at any ISA level, not just ISA 4.
1997-01-08For NEC 4300 project, fix last remaining host/target endianness problemJim Wilson1-1/+1
* gencode.c (build_instruction): Use BigEndianCPU instead of ByteSwapMem.
1996-12-28 * gencode.c (build_instruction): Work around MSVC++ code gen bugMark Alexander1-1/+6
that messes up arithmetic shifts.
1996-12-19 * gencode.c (build_instruction) [MUL]: Cast operands to word64, toIan Lance Taylor1-1/+6
force a 64 bit multiplication. (build_instruction) [OR]: In mips16 mode, don't do anything if the destination register is 0, since that is the default mips16 nop instruction.
1996-12-16 * gencode.c (MIPS16_DECODE): SWRASP is I8, not RI.Ian Lance Taylor1-10/+13
(build_endian_shift): Don't check proc64. (build_instruction): Always set memval to uword64. Cast op2 to uword64 when shifting it left in memory instructions. Always use the same code for stores--don't special case proc64.
1996-12-16 * gencode.c (build_mips16_operands): Fix base PC value for PCIan Lance Taylor1-3/+6
relative operands. (build_instruction): Call JALDELAYSLOT rather than DELAYSLOT for a jal instruction. * interp.c (simJALDELAYSLOT): Define. (JALDELAYSLOT): Define. (INDELAYSLOT, INJALDELAYSLOT): Define. (simulate): Clear simJALDELAYSLOT when simDELAYSLOT is cleared.
1996-12-11For NEC 4100/4300 project: Add little endian support and misc cleanups.Jim Wilson1-1/+1
* gencode.c (build_instruction): Use !ByteSwapMem instead of BigEndianMem. * interp.c (CONFIG, config_EP_{mask,shift,D,DxxDxx, config_BE): Delete. (BigEndianMem): Rename to ByteSwapMem and change sense. (BigEndianCPU, sim_write, LoadMemory, StoreMemory): Change BigEndianMem references to !ByteSwapMem. (set_endianness): New function, with prototype. (sim_open): Call set_endianness. (sim_info): Use simBE instead of BigEndianMem. (xfer_direct_word, xfer_direct_long, swap_direct_word, swap_direct_long, xfer_big_word, xfer_big_long, xfer_little_word, xfer_little_long, swap_word, swap_long): Delete unnecessary MSC_VER ifdefs, keeping the prototype declaration. (swap_word): Rewrite correctly. (ColdReset): Delete references to CONFIG. Delete endianness related code; moved to set_endianness.
1996-12-10For NEC 4100/4300 projectJim Wilson1-0/+3
* gencode.c (build_instruction, case JUMP): Truncate PC to 32 bits. * interp.c (CHECKHILO): Define away. (simSIGINT): New macro. (membank_size): Increase from 1MB to 2MB. (control_c): New function. (sim_resume): Rename parameter signal to signal_number. Add local variable prev. Call signal before and after simulate. (sim_stop_reason): Add simSIGINT support. (sim_warning, sim_error, dotrace, SignalException): Define as stdarg functions always. (sim_warning): Delete call to SignalException. Do call printf_filtered if logfh is NULL. (AddressTranslation): Add #ifdef DEBUG around debugging message and a call to sim_warning.
1996-11-27 * gencode.c (process_instructions): If ! proc64, skip DOUBLEWORDIan Lance Taylor1-0/+3
16 bit instructions.
1996-11-26 Add support for mips16 (16 bit MIPS implementation):Ian Lance Taylor1-1062/+1595
* gencode.c (inst_type): Add mips16 instruction encoding types. (GETDATASIZEINSN): Define. (MIPS_DECODE): Add REG flag to dsllv, dsrav, and dsrlv. Add jalx. Add LEFT flag to mfhi and mflo. Add RIGHT flag to mthi and mtlo. (MIPS16_DECODE): New table, for mips16 instructions. (bitmap_val): New static function. (struct mips16_op): Define. (mips16_op_table): New table, for mips16 operands. (build_mips16_operands): New static function. (process_instructions): If PC is odd, decode a mips16 instruction. Break out instruction handling into new build_instruction function. (build_instruction): New static function, broken out of process_instructions. Check modifiers rather than flags for SHIFT bit count and m[ft]{hi,lo} direction. (usage): Pass program name to fprintf. (main): Remove unused variable this_option_optind. Change ``*loptarg++'' to ``loptarg++''. (my_strtoul): Parenthesize && within ||. * interp.c (sim_trace): If tracefh is NULL, set it to stderr. (LoadMemory): Accept a halfword pAddr if vAddr is odd. (simulate): If PC is odd, fetch a 16 bit instruction, and increment PC by 2 rather than 4. * configure.in: Add case for mips16*-*-*. * configure: Rebuild.
1996-11-20 * Makefile.in: Delete stuff moved to ../common/Make-common.in.David Edelsohn1-4/+0
(SIM_{OBJS,EXTRA_CFLAGS,EXTRA_CLEAN}): Define. * configure.in: Simplify using macros in ../common/aclocal.m4. * configure: Regenerated. * tconfig.in: New file.
1996-09-26Thu Sep 26 17:35:00 1996 James G. Smith <jsmith@cygnus.co.uk>Jackie Smith Cashion1-3/+3
* interp.c (SignalException): Check for explicit terminating breakpoint value. * gencode.c: Pass instruction value through SignalException() calls for Trap, Breakpoint and Syscall.
1996-09-20 * gencode.c (process_instructions): Call build_endian_shift whenIan Lance Taylor1-0/+1
expanding STORE RIGHT, to fix swr. * support.h (SIGNEXTEND): If the sign bit is not set, explicitly clear the high bits. * interp.c (Convert): Fix fmt_single to fmt_long to not truncate. Fix float to int conversions to produce signed values.
1996-09-20Fix multiplication, ldxc1, and floating point conversion. See ChangeLog.Ian Lance Taylor1-11/+45
1996-09-19 * gencode.c (process_instructions): Correct shift count for 32Ian Lance Taylor1-3/+6
bit shift instructions. Correct sign extension for arithmetic shifts to not shift the number of bits in the type.
1996-09-19 * gencode.c (process_instructions): Correct handling of norIan Lance Taylor1-1/+1
instruction.
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