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path: root/sim/mips/gencode.c
AgeCommit message (Expand)AuthorFilesLines
1998-05-21gencode.c: Mark BEGEZALL as LIKELY.Gavin Romig-Koch1-1/+1
1998-04-21For new IGEN simulators, rewrite checks validating correct use of theAndrew Cagney1-15/+0
1997-12-11 * mips.igen (MSUB): Fix to work like MADD.Jeff Law1-1/+6
1997-11-06Replace global IPC with function argument cia or current instructionAndrew Cagney1-1/+1
1997-10-29 * gencode.c: Add tx49 configury and insns.Gavin Romig-Koch1-6/+44
1997-10-25 * sim/mips/gencode.c (build_instruction): Follow sim_write's lead in usingGavin Romig-Koch1-1/+1
1997-10-24Add function to fetch 32bit instructionsAndrew Cagney1-8/+8
1997-10-16Move register definitions and macros out of interp.c and into sim-main.hAndrew Cagney1-1/+1
1997-10-16* gencode.c (build_instruction): Use FPR_STATE not fpr_state.Andrew Cagney1-6/+6
1997-10-16* gencode.c (build_instruction): For "FPSQRT", output correct numberAndrew Cagney1-1/+3
1997-10-14o Add support for configuring wordsize, fp hardware and targetAndrew Cagney1-9/+9
1997-09-25Add/use SIM_AC_OPTION_BITSIZE.Andrew Cagney1-10/+34
1997-09-25Allow gencode.c to generate input to the igen generator.Andrew Cagney1-201/+476
1997-09-20Add handling for 3900's SDBBP, DERET, and RFE insns.Gavin Romig-Koch1-7/+7
1997-09-19 * gencode.c: Add r3900 (tx39).Gavin Romig-Koch1-21/+31
1997-09-16 * sim/mips/gencode.c (build_instruction): Don't need to subtract 4 forGavin Romig-Koch1-1/+2
1997-09-09Remove GCC specific `0x...LL', replace with SIGNED64 (0x...).Andrew Cagney1-14/+11
1997-09-07tx19 and related necessary changes.Gavin Romig-Koch1-0/+9
1997-09-01Test/fix pabsh, pabsw, psrlvw.Andrew Cagney1-5/+9
1997-08-25Add ABFD argument to sim_open call. Pass through to sim_config soAndrew Cagney1-3/+0
1997-07-28Handle overflow from signed divide by -1.Andrew Cagney1-5/+24
1997-07-25gencode.c: Two arg MADD should not assign result to /bin/bash.Gavin Romig-Koch1-1/+2
1997-07-11Fix a number of problems in the r5900 specific p* (parallel) instructions.Andrew Cagney1-88/+129
1997-07-02 * gencode.c (build_instruction): Handle "pext5" according toJeff Law1-1/+1
1997-07-02 * gencode.c (build_instruction): Handle "ppac5" according toJeff Law1-1/+1
1997-07-02 * gencode.c (FEATURE_WARNINGS): Remove FEATURE_WARN_ZERO.Jeff Law1-2/+8
1997-06-02o Fix padd insnAndrew Cagney1-8/+12
1997-05-21Watchpoint interface.Andrew Cagney1-8/+8
1997-04-21for DIV: check for div by zero and int overflowGavin Romig-Koch1-15/+38
1997-02-26Correct the overloaded DOUBLEWORD problemGavin Romig-Koch1-7/+7
1997-02-25start-sanitize-r5900Dawn Perchik1-0/+2
1997-02-20Correct test for ISA dependent bitsGavin Romig-Koch1-6/+18
1997-02-18Correct flags for PMADDUW insnGavin Romig-Koch1-1/+1
1997-02-13 * gencode.c (build_mips16_operands): Correct computation of baseIan Lance Taylor1-1/+1
1997-02-11Add r5900Gavin Romig-Koch1-166/+1499
1997-02-04 * gencode.c (build_instruction): The high order may be set in theIan Lance Taylor1-1/+1
1997-01-08For NEC 4300 project, fix last remaining host/target endianness problemJim Wilson1-1/+1
1996-12-28 * gencode.c (build_instruction): Work around MSVC++ code gen bugMark Alexander1-1/+6
1996-12-19 * gencode.c (build_instruction) [MUL]: Cast operands to word64, toIan Lance Taylor1-1/+6
1996-12-16 * gencode.c (MIPS16_DECODE): SWRASP is I8, not RI.Ian Lance Taylor1-10/+13
1996-12-16 * gencode.c (build_mips16_operands): Fix base PC value for PCIan Lance Taylor1-3/+6
1996-12-11For NEC 4100/4300 project: Add little endian support and misc cleanups.Jim Wilson1-1/+1
1996-12-10For NEC 4100/4300 projectJim Wilson1-0/+3
1996-11-27 * gencode.c (process_instructions): If ! proc64, skip DOUBLEWORDIan Lance Taylor1-0/+3
1996-11-26 Add support for mips16 (16 bit MIPS implementation):Ian Lance Taylor1-1062/+1595
1996-11-20 * Makefile.in: Delete stuff moved to ../common/Make-common.in.David Edelsohn1-4/+0
1996-09-26Thu Sep 26 17:35:00 1996 James G. Smith <jsmith@cygnus.co.uk>Jackie Smith Cashion1-3/+3
1996-09-20 * gencode.c (process_instructions): Call build_endian_shift whenIan Lance Taylor1-0/+1
1996-09-20Fix multiplication, ldxc1, and floating point conversion. See ChangeLog.Ian Lance Taylor1-11/+45
1996-09-19 * gencode.c (process_instructions): Correct shift count for 32Ian Lance Taylor1-3/+6