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2003-01-052003-01-04 Richard Sandiford <rsandifo@redhat.com>Chris Demetriou1-14/+245
Andrew Cagney <ac131313@redhat.com> Gavin Romig-Koch <gavin@redhat.com> Graydon Hoare <graydon@redhat.com> Aldy Hernandez <aldyh@redhat.com> Dave Brolley <brolley@redhat.com> Chris Demetriou <cgd@broadcom.com> * configure.in (mips64vr*): Define TARGET_ENABLE_FR to 1. (sim_mach_default): New variable. (mips64vr-*-*, mips64vrel-*-*): New configurations. Add a new simulator generator, MULTI. * configure: Regenerate. * Makefile.in (SIM_MULTI_OBJ, SIM_EXTRA_DISTCLEAN): New variables. (multi-run.o): New dependency. (SIM_MULTI_ALL, SIM_MULTI_IGEN_CONFIGS): New variables. (tmp-mach-multi, tmp-itable-multi, tmp-run-multi): New rules. (tmp-multi): Combine them. (BUILT_SRC_FROM_MULTI): New variable. Depend on tmp-multi. (clean-extra): Remove sources in BUILT_SRC_FROM_MULTI. (distclean-extra): New rule. * sim-main.h: Include bfd.h. (MIPS_MACH): New macro. * mips.igen (vr4120, vr5400, vr5500): New models. (clo, clz, dclo, dclz, madd, maddu, msub, msub, mul): Add *vr5500. * vr.igen: Replace with new version.
2003-01-052003-01-04 Chris Demetriou <cgd@broadcom.com>Chris Demetriou1-161/+180
* configure.in: Use SIM_AC_OPTION_RESERVED_BITS(1). * configure: Regenerate.
2002-06-16Import current --enable-gdb-build-warnings.Andrew Cagney1-175/+224
2002-06-142002-06-14 Chris Demetriou <cgd@broadcom.com>Chris Demetriou1-1/+1
Ed Satterthwaite <ehs@broadcom.com> * mips3d.igen: New file which contains MIPS-3D ASE instructions. * Makefile.in (IGEN_INCLUDE): Add mips3d.igen. * mips.igen: Include mips3d.igen. (mips3d): New model name for MIPS-3D ASE instructions. (CVT.W.fmt): Don't use this instruction for word (source) format instructions. * cp1.c (fp_binary_r, fp_add_r, fp_mul_r, fpu_inv1, fpu_inv1_32) (fpu_inv1_64, fp_recip1, fp_recip2, fpu_inv_sqrt1, fpu_inv_sqrt1_32) (fpu_inv_sqrt1_64, fp_rsqrt1, fp_rsqrt2): New functions. (NR_FRAC_GUARD, IMPLICIT_1): New macros. * sim-main.h (fmt_pw, CompareAbs, AddR, MultiplyR, Recip1, Recip2) (RSquareRoot1, RSquareRoot2): New macros. (fp_add_r, fp_mul_r, fp_recip1, fp_recip2, fp_rsqrt1) (fp_rsqrt2): New functions. * configure.in: Add MIPS-3D support to mipsisa64 simulator. * configure: Regenerate.
2002-06-032002-06-03 Chris Demetriou <cgd@broadcom.com>Chris Demetriou1-14/+18
Ed Satterthwaite <ehs@broadcom.com> * configure.in (mipsisa64sb1*-*-*): New target for supporting Broadcom SiByte SB-1 processor configurations. * configure: Regenerate. * sb1.igen: New file. * mips.igen: Include sb1.igen. (sb1): New model. * Makefile.in (IGEN_INCLUDE): Add sb1.igen. * mdmx.igen: Add "sb1" model to all appropriate functions and instructions. * mdmx.c (AbsDiffOB, AvgOB, AccAbsDiffOB): New functions. (ob_func, ob_acc): Reference the above. (qh_acc): Adjust to keep the same size as ob_acc. * sim-main.h (status_SBX, MX_VECT_ABSD, MX_VECT_AVG, MX_AbsDiff) (MX_Avg, MX_VECT_ABSDA, MX_AbsDiffC): New macros.
2002-03-122002-03-12 Chris Demetriou <cgd@broadcom.com>Chris Demetriou1-14/+30
* configure.in (mipsisa32*-*-*, mipsisa64*-*-*): New targets. * mips.igen (mips32, mips64): New models, add to all instructions and functions as appropriate. (loadstore_ea, check_u64): New variant for model mips64. (check_fmt_p): New variant for models mipsV and mips64, remove mipsV model marking fro other variant. (SLL) Rename to... (SLLa) this. (CLO, CLZ, MADD, MADDU, MSUB, MSUBU, MUL, SLLb): New instructions for mips32 and mips64. (DCLO, DCLZ): New instructions for mips64.
2000-05-24Change profiling so that it is enabled by default. Re-generate everything.Andrew Cagney1-1/+1
2000-03-02* autoconf correctionFrank Ch. Eigler1-164/+158
* merge from internal repo -> sourceware 2000-03-02 Frank Ch. Eigler <fche@redhat.com> * configure: Regenerated. Tue Feb 8 18:35:01 2000 Donald Lindsay <dlindsay@hound.cygnus.com> * interp.c, mips.igen: all 5 DEADC0DE situations now have sim_io_eprintf calls, conditional on the simulator being in verbose mode.
1999-10-26import gdb-1999-10-25 snapshotJason Molenda1-164/+175
1999-09-09import gdb-1999-09-08 snapshotStan Shebs1-159/+174
1999-07-07import gdb-1999-07-07 pre reformatJason Molenda1-175/+164
1999-05-11import gdb-1999-05-10Stan Shebs1-184/+254
1999-04-26import gdb-19990422 snapshotStan Shebs1-111/+130
1999-04-16Initial creation of sourceware repositorygdb-4_18-branchpointStan Shebs1-0/+4890
1999-04-16Initial creation of sourceware repositoryStan Shebs1-5780/+0
1998-12-30* eCos->devo merge; tx3904 sanitize tags removedFrank Ch. Eigler1-52/+59
1998-12-29 Frank Ch. Eigler <fche@cygnus.com> * interp.c (sim_open): Allocate jm3904 memory in smaller chunks. (load_word): Call SIM_CORE_SIGNAL hook on error. (signal_exception): Call SIM_CPU_EXCEPTION_TRIGGER hook before starting. For exception dispatching, pass PC instead of NULL_CIA. (decode_coproc): Use COP0_BADVADDR to store faulting address. * sim-main.h (COP0_BADVADDR): Define. (SIM_CORE_SIGNAL): Define hook to call mips_core_signal. (SIM_CPU_EXCEPTION*): Define hooks to call mips_cpu_exception*(). (_sim_cpu): Add exc_* fields to store register value snapshots. * mips.igen (*): Replace memory-related SignalException* calls with references to SIM_CORE_SIGNAL hook. * dv-tx3904irc.c (tx3904irc_port_event): printf format warning fix. * sim-main.c (*): Minor warning cleanups.
1998-12-145xxx and elGavin Romig-Koch1-51/+52
1998-12-13for bfd:Gavin Romig-Koch1-1/+1
* archures.c,bfd-in2.h (bfd_mach_mips4121): New. * cpu-mips.c: Added vr4121. * elf32-mips.c (elf_mips_mach): Same. (_bfd_mips_elf_final_write_processing): Same. for gas: * config/tc-mips.c (mips_4121): New. (md_begin,mips_ip,md_longopts,md_parse_option): Add vr4121. for gcc: * config/mips/mips.c (override_options): Add vr4121. * config/mips/t-vr4xxx (MULTILIB_MATCHES): Same. for include/elf: * mips.h (E_MIPS_MACH_4121): New. for include/opcode: * mips.h (INSN_4121): New. for opcodes: * mips-dis.c (set_mips_isa_type): Add bfd_mach_mips4121. (_print_insn_mips): Same. * mips-opc.c: Add vr4121. for sim/mips: * configure.in,mips.igen,vr.igen: Add vr4121. * configure: Rebuilt.
1998-12-12 * configure.in (mips64vr4xxx): Enable TARGET_ENABLE_FR.Gavin Romig-Koch1-255/+211
Set mips_fpu, and mips_fpu_bitsize. Set sim_gen, and sim_igen_machine. * configure: Rebuild. * mips.igen (BC1): Renamed to BC1a and BC1b to avoid conflicts. * sim-main.h (SizeFGR): Handle TARGET_ENABLE_FR.
1998-11-23Configure mips64vr4100-elf nee mips64vr41* as a 64 bit mips16 igen simulator.Andrew Cagney1-52/+55
Fix problems: All vr.igen instructions are 64 bit.
1998-11-23Reconize target mips-tx19-elfAndrew Cagney1-7/+7
1998-11-23Switch mips-lsi-elf mips16 simulator to igen (from gencode).Andrew Cagney1-71/+115
1998-11-12Add configury for mips-lsi-elf target (32 bit MIPS16).Andrew Cagney1-55/+53
Fix numerous problems with PENDING_* code. In old gencode simulator, don't double tick each cycle. Add BREAK instruction to MIPS16 gencode simulator.
1998-10-28Unify (well almost) --enable-build-warnings configuration optionAndrew Cagney1-59/+64
across GDB and SIM directories.
1998-10-27* MONSTER sky -> devo mergeFrank Ch. Eigler1-200/+1163
* ChangeLog / ChangeLog.sky entries were merged with original time stamps; a few were moved between the files
1998-06-04* Early check-in of tx3904 timer sim implementation for ECC.Frank Ch. Eigler1-1/+1
It is not yet properly tested. Thu Jun 4 15:37:33 1998 Frank Ch. Eigler <fche@cygnus.com> * dv-tx3904tmr.c: New file - implements tx3904 timer. * dv-tx3904{irc,cpu}.c: Mild reformatting. * configure.in: Include tx3904tmr in hw_device list. * configure: Rebuilt. * interp.c (sim_open): Instantiate three timer instances. Fix address typo of tx3904irc instance.
1998-05-29Match mips*tx39 not mipst*tx39.Andrew Cagney1-204/+190
1998-05-18* Monster patch - may destablize MIPS sims for a little while.Frank Ch. Eigler1-141/+269
* Followup patch for SCEI PR 15853 * First check-in of TX3904 interrupt controller devices for ECC. [sanitized] * First implementation of MIPS hardware interrupt emulation. Mon May 18 18:22:42 1998 Frank Ch. Eigler <fche@cygnus.com> * configure.in (SIM_AC_OPTION_HARDWARE): Added common hardware modules. Recognize TX39 target with "mips*tx39" pattern. * configure: Rebuilt. * sim-main.h (*): Added many macros defining bits in TX39 control registers. (SignalInterrupt): Send actual PC instead of NULL. (SignalNMIReset): New exception type. * interp.c (board): New variable for future use to identify a particular board being simulated. (mips_option_handler,mips_options): Added "--board" option. (interrupt_event): Send actual PC. (sim_open): Make memory layout conditional on board setting. (signal_exception): Initial implementation of hardware interrupt handling. Accept another break instruction variant for simulator exit. (decode_coproc): Implement RFE instruction for TX39. (mips.igen): Decode RFE instruction as such. start-sanitize-tx3904 * configure.in (tx3904cpu,tx3904irc): Added devices for tx3904. * interp.c: Define "jmr3904" and "jmr3904debug" board types and bbegin to implement memory map. * dv-tx3904cpu.c: New file. * dv-tx3904irc.c: New file. end-sanitize-tx3904
1998-04-26 * configure: Regenerated to track ../common/aclocal.m4 changes.Tom Tromey1-138/+139
* config.in: Ditto. * acconfig.h: New file. * configure.in: Reverted change of Apr 24; use sinclude again.
1998-04-24 * configure: Regenerated to track ../common/aclocal.m4 changes.Tom Tromey1-57/+1788
* config.in: Ditto. * configure.in: Don't call sinclude.
1998-04-05aclocal.m4: Don't enable inlining when cross-compiling.Andrew Cagney1-26/+31
mips/*: Tune mips simulator - allow all memory transfer code to be inlined.
1998-04-04Cleanup INLINE support for simulators using common framework.Andrew Cagney1-71/+76
Make IGEN responsible for co-ordinating inlining of generated files. By default, aclocal.m4 disabled all inlining.
1998-03-30 * configure.in (mipstx39*-*-*): Use gencode simulator ratherGavin Romig-Koch1-73/+69
than igen one. * configure : Rebuild.
1998-03-25Re-do --enable-sim-hardware so that each simulator can specify the devicesAndrew Cagney1-55/+59
it wants built. Generate hw-config.h.
1998-03-18* Added --with-sim-gpu2=<path> option for linking SCEI's GPU2 library withFrank Ch. Eigler1-57/+410
the stand-alone executable. [in ChangeLog.sky:] * sky-gpuif.c (call_gs): Call properly into GPU2 library if configured --with-sim-gpu2. Use SKY_GPU2_REFRESH symbol as placeholder for future GPU2-refresh policy. [in ChangeLog:] * Makefile.in (MIPS_EXTRA_LIBS, SIM_EXTRA_LIBS): Added configurable settings for stand-alone simulator. start-sanitize-sky * configure.in: Added --with-sim-gpu2 option to specify path of sky GPU2 library. Triggers -DSKY_GPU2 for sky-gpuif.c, and links/compiles stand-alone simulator with this library. * interp.c (MEM_SIZE): Increased default sky memory size to 16MB. end-sanitize-sky * configure.in: Added X11 search, just in case. * configure: Regenerated.
1998-02-23sim-main.h: Re-arange r5900 registers so that they have their ownAndrew Cagney1-64/+74
little struct. interp.c: Update. Also add floating point Max/Min functions. mips.igen: Remove r5900 tag from any floating point instructions. r5900.igen: Rewrite. Implement *all* floating point insns (except ld/st). r5400.igen: Tag mdmx functions as being mdmx specific.
1998-02-06 * Makefile.in (SIM_SKY_OBJS,MIPS_EXTRA_OBJS): New vars.Doug Evans1-55/+68
(SIM_OBJS): Add $(MIPS_EXTRA_OBJS). * configure.in: Set mips_extra_objs to sky files if mips64r59*-sky-*. * configure: Regenerated.
1998-02-03IGEN - Replace IMEM (IMEM_IMMED) macro with IMEM<insn-size> macro,Andrew Cagney1-16/+40
update v850, tic80 and mips simulators. IGEN - Prepend prefix to more generated symbols and macros (idecode_issue, instruction_word). IGEN - Add -Wnowith option to supress warnings about word size inflicts in input files. MIPS - Clean up Makefile.in, m16.igen, m16.dc (new), m16run.c (new) so that a mips16 simulator built using IGEN can be compiled.
1998-02-02Add support for configuring the size of the floating point unit (fp_word).Andrew Cagney1-11/+22
For mips, move fp_registers into a separate array of type fp_word[].
1998-02-01mips: Add multi-processor support for r5900. Others might work.Andrew Cagney1-46/+79
common, igen: Fix MP related bugs.
1998-01-31Add config support for the size of the target address and OF cell.Andrew Cagney1-24/+49
1998-01-31mips - for r5900 generate igen simulator.Andrew Cagney1-9/+10
igen - stop crash when simulator isn't multi-sim'ed
1998-01-21Use macro GPR_SET(N,VAL) to clear zero registers.Andrew Cagney1-65/+63
1998-01-20* aclocal.m4: Recognize --enable-maintainer-mode.Doug Evans1-47/+69
*/configure: Regenerated.
1997-12-12 * configure.in (sim_igen_filter): Multi-sim vr5000 - vr5000 orJeff Law1-42/+43
vr5400 with the vr5000 as the default.
1997-12-04Regenerate configure files.Doug Evans1-72/+118
1997-10-29 * gencode.c: Add tx49 configury and insns.Gavin Romig-Koch1-9/+12
* configure.in: Add tx49 configury. * configure: Update.
1997-10-27Separate r5900 specifoc and mips16 instructions.Andrew Cagney1-12/+26
Add support for this to configure (vr5400 target only)
1997-10-27Add mips64vr5400 to configuration listAndrew Cagney1-11/+14
Mark mipsIV instructions as being implemented by the vr5400. Sanitize.
1997-10-24Add basic igen configuration to autoconf. Disable.Andrew Cagney1-9/+27
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