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2000-05-24Change profiling so that it is enabled by default. Re-generate everything.Andrew Cagney1-1/+1
2000-03-02* autoconf correctionFrank Ch. Eigler1-164/+158
1999-10-26import gdb-1999-10-25 snapshotJason Molenda1-164/+175
1999-09-09import gdb-1999-09-08 snapshotStan Shebs1-159/+174
1999-07-07import gdb-1999-07-07 pre reformatJason Molenda1-175/+164
1999-05-11import gdb-1999-05-10Stan Shebs1-184/+254
1999-04-26import gdb-19990422 snapshotStan Shebs1-111/+130
1999-04-16Initial creation of sourceware repositorygdb-4_18-branchpointStan Shebs1-0/+4890
1999-04-16Initial creation of sourceware repositoryStan Shebs1-5780/+0
1998-12-30* eCos->devo merge; tx3904 sanitize tags removedFrank Ch. Eigler1-52/+59
1998-12-145xxx and elGavin Romig-Koch1-51/+52
1998-12-13for bfd:Gavin Romig-Koch1-1/+1
1998-12-12 * configure.in (mips64vr4xxx): Enable TARGET_ENABLE_FR.Gavin Romig-Koch1-255/+211
1998-11-23Configure mips64vr4100-elf nee mips64vr41* as a 64 bit mips16 igen simulator.Andrew Cagney1-52/+55
1998-11-23Reconize target mips-tx19-elfAndrew Cagney1-7/+7
1998-11-23Switch mips-lsi-elf mips16 simulator to igen (from gencode).Andrew Cagney1-71/+115
1998-11-12Add configury for mips-lsi-elf target (32 bit MIPS16).Andrew Cagney1-55/+53
1998-10-28Unify (well almost) --enable-build-warnings configuration optionAndrew Cagney1-59/+64
1998-10-27* MONSTER sky -> devo mergeFrank Ch. Eigler1-200/+1163
1998-06-04* Early check-in of tx3904 timer sim implementation for ECC.Frank Ch. Eigler1-1/+1
1998-05-29Match mips*tx39 not mipst*tx39.Andrew Cagney1-204/+190
1998-05-18* Monster patch - may destablize MIPS sims for a little while.Frank Ch. Eigler1-141/+269
1998-04-26 * configure: Regenerated to track ../common/aclocal.m4 changes.Tom Tromey1-138/+139
1998-04-24 * configure: Regenerated to track ../common/aclocal.m4 changes.Tom Tromey1-57/+1788
1998-04-05aclocal.m4: Don't enable inlining when cross-compiling.Andrew Cagney1-26/+31
1998-04-04Cleanup INLINE support for simulators using common framework.Andrew Cagney1-71/+76
1998-03-30 * configure.in (mipstx39*-*-*): Use gencode simulator ratherGavin Romig-Koch1-73/+69
1998-03-25Re-do --enable-sim-hardware so that each simulator can specify the devicesAndrew Cagney1-55/+59
1998-03-18* Added --with-sim-gpu2=<path> option for linking SCEI's GPU2 library withFrank Ch. Eigler1-57/+410
1998-02-23sim-main.h: Re-arange r5900 registers so that they have their ownAndrew Cagney1-64/+74
1998-02-06 * Makefile.in (SIM_SKY_OBJS,MIPS_EXTRA_OBJS): New vars.Doug Evans1-55/+68
1998-02-03IGEN - Replace IMEM (IMEM_IMMED) macro with IMEM<insn-size> macro,Andrew Cagney1-16/+40
1998-02-02Add support for configuring the size of the floating point unit (fp_word).Andrew Cagney1-11/+22
1998-02-01mips: Add multi-processor support for r5900. Others might work.Andrew Cagney1-46/+79
1998-01-31Add config support for the size of the target address and OF cell.Andrew Cagney1-24/+49
1998-01-31mips - for r5900 generate igen simulator.Andrew Cagney1-9/+10
1998-01-21Use macro GPR_SET(N,VAL) to clear zero registers.Andrew Cagney1-65/+63
1998-01-20* aclocal.m4: Recognize --enable-maintainer-mode.Doug Evans1-47/+69
1997-12-12 * configure.in (sim_igen_filter): Multi-sim vr5000 - vr5000 orJeff Law1-42/+43
1997-12-04Regenerate configure files.Doug Evans1-72/+118
1997-10-29 * gencode.c: Add tx49 configury and insns.Gavin Romig-Koch1-9/+12
1997-10-27Separate r5900 specifoc and mips16 instructions.Andrew Cagney1-12/+26
1997-10-27Add mips64vr5400 to configuration listAndrew Cagney1-11/+14
1997-10-24Add basic igen configuration to autoconf. Disable.Andrew Cagney1-9/+27
1997-10-14o Add support for configuring wordsize, fp hardware and targetAndrew Cagney1-93/+209
1997-09-23Remove need to update <targ>/Makefile.in when adding optional optionsAndrew Cagney1-61/+148
1997-09-22Add memory alignment config option.Andrew Cagney1-44/+104
1997-09-15Update to reflect change to sim/common/aclocal.m4 (allow sim/commonAndrew Cagney1-17/+20
1997-09-05* configure: Regenerated to track ../common/aclocal.m4 changes.David Edelsohn1-11/+12
1997-08-27Fix doco on enable-sim-inline.Andrew Cagney1-1/+1