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2015-12-27sim: unify sim-hloadMike Frysinger1-1/+0
Pretty much all targets are using this module already, so add it to the common list of objects. The only oddball out here is cris and that's because it supports loading via an offset for all the phdrs. We drop support for that.
2015-11-16sim: sim-stop/sim-reason/sim-reg: move to common obj listMike Frysinger1-2/+0
Now that all arches (for the most part) have moved over, move sim-stop.o, sim-reason.o, and sim-reg.o to the common object list and out of all the arch ports.
2015-09-25[PATCH] Add micromips support to the MIPS simulatorAndrew Bennett1-40/+284
2015-09-25 Andrew Bennett <andrew.bennett@imgtec.com> Ali Lown <ali.lown@imgtec.com> sim/common/ * sim-bits.h (EXTEND6): New macro. (EXTEND12): New macro. (EXTEND25): New macro. sim/mips/ * Makefile.in (tmp-micromips): New rule. (tmp-mach-multi): Add support for micromips. * configure.ac (mips*-sde-elf* | mips*-mti-elf*): Made a multi sim that works for both mips64 and micromips64. (mipsisa32r2*-*-*): Made a multi sim that works for mips32 and micromips32. Add build support for micromips. * dsp.igen (do_ph_s_absq, do_w_s_absq, do_qb_s_absq, do_addsc, do_addwc, do_bitrev, do_extpv, do_extrv, do_extrv_s_h, do_insv, do_lxx do_modsub, do_mthlip, do_mulsaq_s_w_ph, do_ph_packrl, do_qb_pick do_ph_pick, do_qb_ph_precequ, do_qb_ph_preceu, do_w_preceq do_w_ph_precrq, do_ph_qb_precrq, do_w_ph_rs_precrq do_qb_w_raddu, do_rddsp, do_repl, do_shilov, do_ph_shl, do_qb_shl do_w_s_shllv, do_ph_shrlv, do_w_r_shrav, do_wrdsp, do_qb_shrav, do_append, do_balign, do_ph_w_mulsa, do_ph_qb_precr, do_prepend): New functions. Refactored instruction code to use these functions. * dsp2.igen: Refactored instruction code to use the new functions. * interp.c (decode_coproc): Refactored to work with any instruction encoding. (isa_mode): New variable (RSVD_INSTRUCTION): Changed to 0x00000039. * m16.igen (BREAK16): Refactored instruction to use do_break16. (JALX32): Add mips32, mips64, mips32r2 and mips64r2 models. * micromips.dc: New file. * micromips.igen: New file. * micromips16.dc: New file. * micromipsdsp.igen: New file. * micromipsrun.c: New file. * mips.igen (do_swc1): Changed to work with any instruction encoding. (do_add do_addi do_andi do_dadd do_daddi do_dsll32 do_dsra32 do_dsrl32, do_dsub, do_break, do_break16, do_clo, do_clz, do_dclo do_dclz, do_lb, do_lh, do_lwr, do_lwl, do_lwc, do_lw, do_lwu, do_lhu do_ldc, do_lbu, do_ll, do_lld, do_lui, do_madd, do_dsp_madd, do_maddu do_dsp_maddu, do_dsp_mfhi, do_dsp_mflo, do_movn, do_movz, do_msub do_dsp_msub, do_msubu, do_dsp_msubu, do_mthi, do_dsp_mthi, do_mtlo do_dsp_mtlo, do_mul, do_dsp_mult, do_dsp_multu, do_pref, do_sc, do_scd do_sub, do_sw, do_teq, do_teqi, do_tge, do_tgei, do_tgeiu, do_tgeu, do_tlt do_tlti, do_tltiu, do_tltu, do_tne, do_tnei, do_abs_fmt, do_add_fmt do_alnv_ps, do_c_cond_fmt, do_ceil_fmt, do_cfc1, do_ctc1, do_cvt_d_fmt do_cvt_l_fmt, do_cvt_ps_s, do_cvt_s_fmt, do_cvt_s_pl, do_cvt_s_pu do_cvt_w_fmt, do_div_fmt, do_dmfc1b, do_dmtc1b, do_floor_fmt, do_luxc1_32 do_luxc1_64, do_lwc1, do_lwxc1, do_madd_fmt, do_mfc1b, do_mov_fmt, do_movtf do_movtf_fmt, do_movn_fmt, do_movz_fmt, do_msub_fmt, do_mtc1b, do_mul_fmt do_neg_fmt, do_nmadd_fmt, do_nmsub_fmt, do_pll_ps, do_plu_ps, do_pul_ps do_puu_ps, do_recip_fmt, do_round_fmt, do_rsqrt_fmt, do_prefx, do_sdc1 do_suxc1_32, do_suxc1_64, do_sqrt_fmt, do_sub_fmt, do_swc1, do_swxc1 do_trunc_fmt): New functions, refactored from existing instructions. Refactored instruction code to use these functions. (RSVD): Changed to use new reserved instruction. (loadstore_ea, not_word_value, unpredictable, check_mt_hilo, check_mf_hilo, check_mult_hilo, check_div_hilo, check_u64, do_luxc1_32, do_sdc1, do_suxc1_32, check_fmt_p, check_fpu, do_load_double, do_store_double): Added micromips32 and micromips64 models. Added include for micromips.igen and micromipsdsp.igen Add micromips32 and micromips64 models. (DecodeCoproc): Updated to use new macro definition. * mips3264r2.igen (do_dsbh, do_dshd, do_dext, do_dextm, do_dextu, do_di, do_dins, do_dinsm, do_ei, do_ext, do_mfhc1, do_mthc1, do_ins, do_dinsu, do_seb, do_seh do_rdhwr, do_wsbh): New functions. Refactored instruction code to use these functions. * sim-main.h (CP0_operation): New enum. (DecodeCoproc): Updated macro. (IMEM32_MICROMIPS, IMEM16_MICROMIPS, MICROMIPS_MINOR_OPCODE, MICROMIPS_DELAYSLOT_SIZE_ANY, MICROMIPS_DELAYSLOT_SIZE_16, MICROMIPS_DELAYSLOT_SIZE_32, ISA_MODE_MIPS32 and ISA_MODE_MICROMIPS): New defines. (sim_state): Add isa_mode field. sim/testsuite/sim/mips/ * basic.exp (run_micromips_test, run_sim_tests): New functions Add support for micromips tests. * hilo-hazard-4.s: New file. * testutils.inc (_dowrite): Changed reserved instruction encoding. (writemsg): Moved the la and li instructions before the data they are assigned to, which prevents a bug where MIPS32 relocations are used instead of micromips relocations when building for micromips.
2015-04-15sim: unify sim-cpu usageMike Frysinger1-1/+0
Now that all the targets are utilizing CPU_PC_{FETCH,STORE}, and the cpu state is multicore, and the STATE_CPU defines match, we can move it all to the common code.
2015-04-13sim: mips: convert to sim-cpuMike Frysinger1-0/+1
Make cpu allocation fully dynamic so we can leverage the common sim-cpu and its APIs.
2015-04-12sim: arm/mips: fix sim_read/sim_write linkage errorsMike Frysinger1-1/+1
With sim-hrw.o being built & linked in the common list, some people are getting linking errors now for these targets. Move the main objects that provide these functions before the common list to avoid that.
2015-04-06sim: move sim-engine.o/sim-hrw.o to the common listMike Frysinger1-1/+0
This makes these two objects available to all sims by default.
2015-03-23sim: dv-sockser: move build to common dirMike Frysinger1-2/+0
If dv-sockser is available, lets add it to the common SIM_HW_OBJS variable so it is always included automatically. Now ports do not have to shoe horn it in directly themselves. It does mean it will be compiled for targets that don't explicitly use it, but that's really what we want anyways.
2015-03-14sim: make nrun the default run programMike Frysinger1-4/+0
We want people to stop using the run.c frontend, but it's hard to notice when it's still set as the default. Lets flip things so nrun.c is the default, and users of run.c will get an error by default. We turn that error into a warning for existing sims so we don't break them -- this is mostly meant for people starting new ports.
2011-07-08 * Makefile.in ($(SIM_MULTI_OBJ)): Depend on sim-main.hHans-Peter Nilsson1-0/+2
$(SIM_EXTRA_DEPS).
2011-07-08 * Makefile.in (tmp-mach-multi): Exit early when igen fails.Hans-Peter Nilsson1-1/+1
2007-06-25sim/mips/Richard Sandiford1-0/+1
* Makefile.in (m16_run.o): New rule.
2007-02-20 [ gas/ChangeLog ]Thiemo Seufer1-0/+1
* config/tc-mips.c (mips_set_options, mips_opts, file_ase_dspr2, ISA_SUPPORTS_DSPR2_ASE, MIPS_CPU_ASE_DSPR2): Add DSP R2 ASE support. (macro_build): Add case '2'. (macro): Expand M_BALIGN to nop, packrl.ph or balign. (validate_mips_insn): Add support for balign instruction. (mips_ip): Handle DSP R2 instructions. Support balign instruction. (OPTION_DSPR2, OPTION_NO_DSPR2, OPTION_COMPAT_ARCH_BASE, md_parse_option, mips_after_parse_args): Add -mdspr2 and -mno-dspr2 command line options. (s_mipsset): Add support for .set dspr2 and .set nodspr2 directives. (md_show_usage): Add -mdspr2 and -mno-dspr2 help output. * doc/c-mips.texi, doc/as.texinfo: Document -mdspr2, -mno-dspr2, .set dspr2, .set nodspr2. [ gas/testsuite/ChangeLog ] * gas/mips/mips32-dspr2.s, gas/mips/mips32-dspr2.d: New test for DSP R2. * gas/mips/mips.exp: Run new test. [ include/opcode/Changelog ] * mips.h (OP_SH_BP, OP_MASK_BP): Add support for balign instruction. (INSN_DSPR2): Add flag for DSP R2 instructions. (M_BALIGN): New macro. [ opcodes/ChangeLog ] * mips-dis.c (mips_arch_choices): Add DSP R2 support. (print_insn_args): Add support for balign instruction. * mips-opc.c (D33): New shortcut for DSP R2 instructions. (mips_builtin_opcodes): Add DSP R2 instructions. [ sim/mips/ChangeLog ] * Makefile.in (IGEN_INCLUDE): Add dsp2.igen. * configure.ac (mips*-sde-elf*, mipsisa32r2*-*-*, mipsisa64r2*-*-*): Add dsp2 to sim_igen_machine. * configure: Regenerate. * dsp.igen (do_ph_op): Add MUL support when op = 2. (do_ph_mulq): New function to support mulq_rs.ph and mulq_s.ph. (mulq_rs.ph): Use do_ph_mulq. (MFHI, MFLO, MTHI, MTLO): Move these instructions to mips.igen. * mips.igen: Add dsp2 model and include dsp2.igen. (MFHI, MFLO, MTHI, MTLO): Extend these instructions for for *mips32r2, *mips64r2, *dsp. (MADD, MADDU, MSUB, MSUBU, MULT, MULTU): Extend these instructions for *mips32r2, *mips64r2, *dsp2. * dsp2.igen: New file for MIPS DSP REV 2 ASE. [ sim/testsuite/sim/mips/ChangeLog ] * basic.exp: Run the dsp2 test. * utils-dsp.inc (dspckacc_astio, dspck_tsimm): New macro. * mips32-dsp2.s: New test.
2006-08-29 * Makefile.in (IGEN_INCLUDE): Add missing includes for m16e.igen andThiemo Seufer1-1/+10
mips3264r2.igen. Add missing dependency rules. * m16e.igen: Support for mips16e save/restore instructions.
2005-12-14* Makefile.in (SIM_OBJS): Add dsp.o.Chao-ying Fu1-0/+4
(dsp.o): New dependency. (IGEN_INCLUDE): Add dsp.igen. * configure.ac (mipsisa32r2*-*-*, mipsisa32*-*-*, mipsisa64r2*-*-*, mipsisa64*-*-*): Add dsp to sim_igen_machine. * configure: Regenerate. * mips.igen: Add dsp model and include dsp.igen. (MFHI, MFLO, MTHI, MTLO): Remove mips32, mips32r2, mips64, mips64r2, because these instructions are extended in DSP ASE. * sim-main.h (LAST_EMBED_REGNUM): Change from 89 to 96 because of adding 6 DSP accumulator registers and 1 DSP control register. (AC0LOIDX, AC0HIIDX, AC1LOIDX, AC1HIIDX, AC2LOIDX, AC2HIIDX, AC3LOIDX, AC3HIIDX, DSPLO, DSPHI, DSPCRIDX, DSPCR, DSPCR_POS_SHIFT, DSPCR_POS_MASK, DSPCR_POS_SMASK, DSPCR_SCOUNT_SHIFT, DSPCR_SCOUNT_MASK, DSPCR_SCOUNT_SMASK, DSPCR_CARRY_SHIFT, DSPCR_CARRY_MASK, DSPCR_CARRY_SMASK, DSPCR_CARRY, DSPCR_EFI_SHIFT, DSPCR_EFI_MASK, DSPCR_EFI_SMASK, DSPCR_EFI, DSPCR_OUFLAG_SHIFT, DSPCR_OUFLAG_MASK, DSPCR_OUFLAG_SMASK, DSPCR_OUFLAG4, DSPCR_OUFLAG5, DSPCR_OUFLAG6, DSPCR_OUFLAG7, DSPCR_CCOND_SHIFT, DSPCR_CCOND_MASK, DSPCR_CCOND_SMASK): New define. (DSPLO_REGNUM, DSPHI_REGNUM): New array for DSP accumulators. * dsp.c, dsp.igen: New files for MIPS DSP ASE.
2003-05-16Use $(SHELL) whenever we invoke move-if-change.Ian Lance Taylor1-52/+54
2003-01-062003-01-05 Richard Sandiford <rsandifo@redhat.com>Chris Demetriou1-1/+1
* Makefile.in (tmp-run-multi): Fix mips16 filter.
2003-01-052003-01-04 Richard Sandiford <rsandifo@redhat.com>Chris Demetriou1-0/+94
Andrew Cagney <ac131313@redhat.com> Gavin Romig-Koch <gavin@redhat.com> Graydon Hoare <graydon@redhat.com> Aldy Hernandez <aldyh@redhat.com> Dave Brolley <brolley@redhat.com> Chris Demetriou <cgd@broadcom.com> * configure.in (mips64vr*): Define TARGET_ENABLE_FR to 1. (sim_mach_default): New variable. (mips64vr-*-*, mips64vrel-*-*): New configurations. Add a new simulator generator, MULTI. * configure: Regenerate. * Makefile.in (SIM_MULTI_OBJ, SIM_EXTRA_DISTCLEAN): New variables. (multi-run.o): New dependency. (SIM_MULTI_ALL, SIM_MULTI_IGEN_CONFIGS): New variables. (tmp-mach-multi, tmp-itable-multi, tmp-run-multi): New rules. (tmp-multi): Combine them. (BUILT_SRC_FROM_MULTI): New variable. Depend on tmp-multi. (clean-extra): Remove sources in BUILT_SRC_FROM_MULTI. (distclean-extra): New rule. * sim-main.h: Include bfd.h. (MIPS_MACH): New macro. * mips.igen (vr4120, vr5400, vr5500): New models. (clo, clz, dclo, dclz, madd, maddu, msub, msub, mul): Add *vr5500. * vr.igen: Replace with new version.
2002-06-142002-06-14 Chris Demetriou <cgd@broadcom.com>Chris Demetriou1-0/+1
Ed Satterthwaite <ehs@broadcom.com> * mips3d.igen: New file which contains MIPS-3D ASE instructions. * Makefile.in (IGEN_INCLUDE): Add mips3d.igen. * mips.igen: Include mips3d.igen. (mips3d): New model name for MIPS-3D ASE instructions. (CVT.W.fmt): Don't use this instruction for word (source) format instructions. * cp1.c (fp_binary_r, fp_add_r, fp_mul_r, fpu_inv1, fpu_inv1_32) (fpu_inv1_64, fp_recip1, fp_recip2, fpu_inv_sqrt1, fpu_inv_sqrt1_32) (fpu_inv_sqrt1_64, fp_rsqrt1, fp_rsqrt2): New functions. (NR_FRAC_GUARD, IMPLICIT_1): New macros. * sim-main.h (fmt_pw, CompareAbs, AddR, MultiplyR, Recip1, Recip2) (RSquareRoot1, RSquareRoot2): New macros. (fp_add_r, fp_mul_r, fp_recip1, fp_recip2, fp_rsqrt1) (fp_rsqrt2): New functions. * configure.in: Add MIPS-3D support to mipsisa64 simulator. * configure: Regenerate.
2002-06-032002-06-03 Chris Demetriou <cgd@broadcom.com>Chris Demetriou1-0/+1
Ed Satterthwaite <ehs@broadcom.com> * configure.in (mipsisa64sb1*-*-*): New target for supporting Broadcom SiByte SB-1 processor configurations. * configure: Regenerate. * sb1.igen: New file. * mips.igen: Include sb1.igen. (sb1): New model. * Makefile.in (IGEN_INCLUDE): Add sb1.igen. * mdmx.igen: Add "sb1" model to all appropriate functions and instructions. * mdmx.c (AbsDiffOB, AvgOB, AccAbsDiffOB): New functions. (ob_func, ob_acc): Reference the above. (qh_acc): Adjust to keep the same size as ob_acc. * sim-main.h (status_SBX, MX_VECT_ABSD, MX_VECT_AVG, MX_AbsDiff) (MX_Avg, MX_VECT_ABSDA, MX_AbsDiffC): New macros.
2002-06-032002-06-03 Chris Demetriou <cgd@broadcom.com>Chris Demetriou1-0/+1
* Makefile.in (IGEN_INCLUDE): Add mdmx.igen.
2002-06-022002-06-02 Chris Demetriou <cgd@broadcom.com>Chris Demetriou1-0/+2
Ed Satterthwaite <ehs@broadcom.com> * mips.igen (mdmx): New (pseudo-)model. * mdmx.c, mdmx.igen: New files. * Makefile.in (SIM_OBJS): Add mdmx.o. * sim-main.h (MDMX_accumulator, MX_fmtsel, signed24, signed48): New typedefs. (ACC, MX_Add, MX_AddA, MX_AddL, MX_And, MX_C_EQ, MX_C_LT, MX_Comp) (MX_FMT_OB, MX_FMT_QH, MX_Max, MX_Min, MX_Msgn, MX_Mul, MX_MulA) (MX_MulL, MX_MulS, MX_MulSL, MX_Nor, MX_Or, MX_Pick, MX_RAC) (MX_RAC_H, MX_RAC_L, MX_RAC_M, MX_RNAS, MX_RNAU, MX_RND_AS) (MX_RND_AU, MX_RND_ES, MX_RND_EU, MX_RND_ZS, MX_RND_ZU, MX_RNES) (MX_RNEU, MX_RZS, MX_RZU, MX_SHFL, MX_ShiftLeftLogical) (MX_ShiftRightArith, MX_ShiftRightLogical, MX_Sub, MX_SubA, MX_SubL) (MX_VECT_ADD, MX_VECT_ADDA, MX_VECT_ADDL, MX_VECT_AND) (MX_VECT_MAX, MX_VECT_MIN, MX_VECT_MSGN, MX_VECT_MUL, MX_VECT_MULA) (MX_VECT_MULL, MX_VECT_MULS, MX_VECT_MULSL, MX_VECT_NOR) (MX_VECT_OR, MX_VECT_SLL, MX_VECT_SRA, MX_VECT_SRL, MX_VECT_SUB) (MX_VECT_SUBA, MX_VECT_SUBL, MX_VECT_XOR, MX_WACH, MX_WACL, MX_Xor) (SIM_ARGS, SIM_STATE, UnpredictableResult, fmt_mdmx, ob_fmtsel) (qh_fmtsel): New macros. (_sim_cpu): New member "acc". (mdmx_acc_op, mdmx_cc_op, mdmx_cpr_op, mdmx_pick_op, mdmx_rac_op) (mdmx_round_op, mdmx_shuffle, mdmx_wach, mdmx_wacl): New functions.
2002-03-202002-03-19 Chris G. Demetriou <cgd@broadcom.com>Chris Demetriou1-0/+2
* interp.c: Move FPU support routines from here to... * cp1.c: Here. New file. * Makefile.in (SIM_OBJS): Add cp1.o to object list. (cp1.o): New target.
2000-07-27Don't clean *.igen.Andrew Cagney1-1/+1
1999-04-16Initial creation of sourceware repositorygdb-4_18-branchpointStan Shebs1-0/+293
1999-04-16Initial creation of sourceware repositoryStan Shebs1-520/+0
1998-12-16New 'hack' generatorGavin Romig-Koch1-33/+204
1998-10-27* MONSTER sky -> devo mergeFrank Ch. Eigler1-9/+10
* ChangeLog / ChangeLog.sky entries were merged with original time stamps; a few were moved between the files
1998-04-14Implement 32 bit MIPS16 instructions listed in m16.igen.Andrew Cagney1-1/+1
1998-04-08* R5900 sky COP2 testing continuing. Today only smallFrank Ch. Eigler1-0/+1
VCALLMS-related were found/fixed. [ChangeLog.sky] * sky-vu.c ({read,write}_vu_special_reg): Add CMSAR[01] as special registers for a VU. Behavior not as mandated. ({read,write}_vu_{misc,special}_reg): Create sim_io_error upon access to unknown register. Behavior not as mandated. * sky-vu.h (anonymous register numbering enum): Add CMSAR[01]. * sky-libvpe.c (indebug): Cache $ENV{'SKY_DEBUG'}. [ChangeLog] * Makefile.in (SIM_SKY_OBJS): Added sky-vudis.o. * interp.c (decode_coproc): Refer to VU CIA as a "special" register, not as a "misc" register. Aha. Add activity assertions after VCALLMS* instructions.
1998-04-05aclocal.m4: Don't enable inlining when cross-compiling.Andrew Cagney1-7/+9
mips/*: Tune mips simulator - allow all memory transfer code to be inlined.
1998-03-27* Inserted skeleton of R5900 COP2 simulation. Merged old vu[01].[ch] codeFrank Ch. Eigler1-2/+0
into single PKE-style vu.[ch]. [ChangeLog] Fri Mar 27 16:19:29 1998 Frank Ch. Eigler <fche@cygnus.com> start-sanitize-sky * Makefile.in (SIM_SKY_OBJS): Replaced sky-vu[01].o with sky-vu.o. * interp.c (sim_{load,store}_register): Use new vu[01]_device static to access VU registers. (decode_coproc): Added skeleton of sky COP2 (VU) instruction decoding. Work in progress. * mips.igen (LDCzz, SDCzz): Removed *5900 case for this overlapping/redundant bit pattern. (LQC2, SQC2): Added *5900 COP2 instruction skeleta. Work in progress. * sim-main.h (status_CU[012]): Added COP[n]-enabled flags for status register. end-sanitize-sky * interp.c (cop_lq, cop_sq): New functions for future 128-bit access to coprocessor registers. * sim-main.h (COP_LQ, COP_SQ): New macro front-ends for above. [ChangeLog.sky] * sky-engine.c (engine_run): Adapted from vu[01] -> vu merge. * sky-hardware.c (register_devices): Ditto * sky-pke.c (pke_fifo_*): Made these functions private again, now that the GPUIF code does not use them. * sky-pke.h (pke_fifo_*): Removed newly private declarations. * sky-vu.c (*): Major rework: merge of old sky-vu0.c and sky-vu1.c. Management of two VU devices parallels two PKEs. Work in progress. * sky-vu.h (*): Other half of merge. (vu_device): New struct, parallel to pke_device.
1998-03-27sky-gs.c: initial drop of GS control registers (outstanding questions)Patrick Macdonald1-0/+1
sky-gs.h: initial drop of GS control registers Makefile.in: added sky-gs.o to sanitized list sky-gpuif.c (gif_io_write_buffer): correct memset length error, renamed trace file for gif
1998-03-27 * sky-vu.c: new file to read/write VU registersRon Unrau1-0/+7
* Makefile.in .Sanitize: add sky-vu.c * sky-vu.h: define registers as enum, export read/write routines * sky-vu[01].[ch]: use register read/write routines in sky-vu.c * interp.c: use register read/write routines in sky-vu.c
1998-03-01sky-gdb.c: new file - temporary demo version of the sim interfaceRon Unrau1-18/+19
sky-hardware.c: add sim commands Makefile.in: build sky-gdb.c
1998-02-06 * Makefile.in (SIM_SKY_OBJS,MIPS_EXTRA_OBJS): New vars.Doug Evans1-0/+16
(SIM_OBJS): Add $(MIPS_EXTRA_OBJS). * configure.in: Set mips_extra_objs to sky files if mips64r59*-sky-*. * configure: Regenerated.
1998-02-03IGEN - Replace IMEM (IMEM_IMMED) macro with IMEM<insn-size> macro,Andrew Cagney1-40/+98
update v850, tic80 and mips simulators. IGEN - Prepend prefix to more generated symbols and macros (idecode_issue, instruction_word). IGEN - Add -Wnowith option to supress warnings about word size inflicts in input files. MIPS - Clean up Makefile.in, m16.igen, m16.dc (new), m16run.c (new) so that a mips16 simulator built using IGEN can be compiled.
1997-11-06IGEN likes to cache the current instruction address (CIA). Change theAndrew Cagney1-0/+6
MIPS simulator so that correctly writes the value of CIA back int PC (the global previously used) when the simulation halts. Fix implementation of DELAY_SLOT and NULLIFY_NEXT_INSTRUCTION macros.
1997-11-05Rewrite the MIPS simulator's memory model so that it uses the genericAndrew Cagney1-0/+1
common/sim-core. Add support for 3, 5, 6, 7 byte transfers to sim core.
1997-10-29common/sim-bits.h: Document ROTn macro.Andrew Cagney1-3/+10
igen/{igen.c,ld-insns.h}: Document mnemonic string formats. mips/Makefile.in: Add dependencies for files included by mips.igen mips/vr5400.igen: checkpoint vr5400 instructions.
1997-10-27Separate r5900 specifoc and mips16 instructions.Andrew Cagney1-4/+5
Add support for this to configure (vr5400 target only)
1997-10-27Add mips64vr5400 to configuration listAndrew Cagney1-19/+23
Mark mipsIV instructions as being implemented by the vr5400. Sanitize.
1997-10-24Add basic igen configuration to autoconf. Disable.Andrew Cagney1-9/+185
1997-10-21Delete profile support from MIPS simulator, use sim/common/sim-profileAndrew Cagney1-0/+1
module instead. Generate a "gmon.out" (gprof) when profiling the target PC. Add target PC profiling option --profile-pc-granularity (bucket size)
1997-10-16Rename generated file engine.c to oengine.c.Andrew Cagney1-4/+4
1997-10-14Move global MIPS simulator variables into sim_cpu struct.Andrew Cagney1-1/+1
1997-10-14o Add support for configuring wordsize, fp hardware and targetAndrew Cagney1-3/+10
endianness. Provide defaults for some tier-1 mips targets. o Parameterize all functions with SIM_DESC.
1997-09-23Remove need to update <targ>/Makefile.in when adding optional optionsAndrew Cagney1-8/+2
to <targ>/configure.in. Simplify logic used to select target [default] endianness.
1997-08-27Add ABFD argument to sim_create_inferior. Document.Andrew Cagney1-3/+40
Add file sim-hload.c - generic load for hardware only simulators. Review each simulators sim_open, sim_load, sim_create_inferior so that they more closely match required behavour.
1997-02-04 * Makefile.in (@COMMON_MAKEFILE_FRAG): UseDavid Edelsohn1-1/+3
COMMON_{PRE,POST}_CONFIG_FRAG instead. * configure.in: sinclude ../common/aclocal.m4. * configure: Regenerated.
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