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1998-10-30* build fix for tx39 sim; caused by sky->devo mergeFrank Ch. Eigler1-0/+7
1998-10-29* sky->devo merge, continued -- left out the r5900 TLB last time!Frank Ch. Eigler1-0/+7
1998-10-29* Fixes for PR 18015, from customer.Frank Ch. Eigler1-0/+7
1998-10-27* MONSTER sky -> devo mergeFrank Ch. Eigler1-0/+69
1998-10-10 * interp.c: #include "itable.h" if WITH_IGEN.Doug Evans1-0/+10
1998-09-10 * r5900.igen (plzcw): Make `i' signed.Doug Evans1-0/+4
1998-09-09Branch merge for GDB:Ron Unrau1-0/+5
1998-09-08* Patch for PR 17142, brought over from sky branch.Frank Ch. Eigler1-0/+11
1998-09-01* Build fixes for tx39 sim hosted on strange Linux boxen.Frank Ch. Eigler1-22/+55
1998-07-25Add new file vr.igen which is a merge of vr5400.igen and vr4320.igen.Andrew Cagney1-0/+31
1998-06-29 * mips.igen (check_mf_hilo): Correct check.Gavin Romig-Koch1-0/+47
1998-06-16* ECC (tx39) and sky changes.Frank Ch. Eigler1-0/+17
1998-06-11* Moving some sky-specific ChangeLog entries into ChangeLog.skyFrank Ch. Eigler1-8/+0
1998-06-10* Support for sky hardware interrupts. The sky-dma cannot triggerFrank Ch. Eigler1-0/+20
1998-06-09* Handle 10 and 20-bit versions of Break instruction. Move handlingIan Carmichael1-0/+10
1998-06-09* Updates to tx3904 peripheral simulations for ECC.Frank Ch. Eigler1-0/+16
1998-06-09 * mips.igen (SWC1) : Correct the handling of ReverseEndianGavin Romig-Koch1-0/+5
1998-06-09 * configure.in (mips_fpu_bitsize) : Set this correctly for 32-bit mipsGavin Romig-Koch1-0/+6
1998-06-04* Early check-in of tx3904 timer sim implementation for ECC.Frank Ch. Eigler1-0/+11
1998-06-04The r5900 doesn't have HI/LO DIV/MUL register problems. HobbleAndrew Cagney1-0/+12
1998-06-02* SYSCALL now uses exception vector.Ian Carmichael1-0/+5
1998-06-01* Small TX39-only patch for ECC.Frank Ch. Eigler1-0/+5
1998-06-01 * r5900.igen (rsqrt.s): Update based on r5900 ISA manual version 2.1.Jeff Law1-0/+7
1998-05-29Match mips*tx39 not mipst*tx39.Andrew Cagney1-0/+14
1998-05-25Fix mips SWL on 64bit ISA when 32 bit word appears in second half ofAndrew Cagney1-0/+7
1998-05-22Only enable H/W on some mips targets.Andrew Cagney1-0/+11
1998-05-22Sanity clauseAndrew Cagney1-2/+2
1998-05-21gencode.c: Mark BEGEZALL as LIKELY.Gavin Romig-Koch1-0/+4
1998-05-21Fix sign extension on 32 bit add/sub instructions.Andrew Cagney1-0/+5
1998-05-21* interp.c (sim_fetch_register): Convert internal r5900 regs toAndrew Cagney1-0/+9
1998-05-18* Monster patch - may destablize MIPS sims for a little while.Frank Ch. Eigler1-0/+31
1998-05-13 * r5900.igen: Replace the calls and the definition of theGavin Romig-Koch1-0/+6
1998-05-13 * tx.igen (madd,maddu): Replace calls to check_op_hiloGavin Romig-Koch1-0/+5
1998-05-13 * mips/mips.igen (check_op_hilo,check_mult_hilo,check_div_hilo):Gavin Romig-Koch1-0/+10
1998-05-12* configure.in (SUBTARGET_R3900): Define for mipstx39 target.Andrew Cagney1-0/+9
1998-05-07 * sim-main.h (INSN_NAME): New arg `cpu'.Doug Evans1-0/+25
1998-04-29Tue Apr 28 18:28:58 1998 Geoffrey Noer <noer@cygnus.com>Geoffrey Noer1-0/+4
1998-04-26 * configure: Regenerated to track ../common/aclocal.m4 changes.Tom Tromey1-0/+10
1998-04-24 * configure: Regenerated to track ../common/aclocal.m4 changes.Tom Tromey1-0/+9
1998-04-24* mips.igen (do_store_left): Pass 0 not NULL to store_memory.Andrew Cagney1-0/+4
1998-04-21Entry about changing sim_open missing from changelog.Andrew Cagney1-0/+2
1998-04-21Implement ERET instruction.Andrew Cagney1-0/+13
1998-04-21For new IGEN simulators, rewrite checks validating correct use of theAndrew Cagney1-0/+48
1998-04-17* Fixed data mangling problems in R5900 COP2 LQC2/SQC2 instructions.Frank Ch. Eigler1-0/+7
1998-04-16* Adapted R5900 COP2 interface code to clarified micro-mode interlockFrank Ch. Eigler1-0/+7
1998-04-16o CVT.S.W and CVT.W.S were reversedAndrew Cagney1-0/+18
1998-04-15TX19 uses igen by default.Andrew Cagney1-1/+8
1998-04-15* Changes to make interp.c compile under mips64r5900-sky-elf target.Frank Ch. Eigler1-0/+7
1998-04-15Re-fix 32 bit DSRAV instruction.Andrew Cagney1-0/+10
1998-04-15Debug tx19 built from igen sources.Andrew Cagney1-0/+26
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